VHDL test bench of Mac

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-- Test bench for Complex MAC
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

LIBRARY bitlib;
USE bitlib.bit_pack.all;

LIBRARY my_vhdl;
USE my_vhdl.c_mac_gate;

ENTITY MAC_test_gate IS
END MAC_test_gate;

ARCHITECTURE tester OF MAC_test_gate IS
        COMPONENT c_mac_gate
                PORT (
                  clk, clr : IN bit;                           -- input
                  x_real   : IN bit_vector(15 downto 0);       -- input
                  x_imag   : IN bit_vector(15 downto 0);       -- input
                  y_real   : IN bit_vector(15 downto 0);       -- input
                  y_imag   : IN bit_vector(15 downto 0);       -- input

                  s_real   : INOUT bit_vector(15 downto 0);      -- output
                  s_imag   : INOUT bit_vector(15 downto 0);      -- output
                  ovf      : OUT bit); 
        END COMPONENT;

        SIGNAL clk         : bit := '0';
        SIGNAL clr         : bit := '1';
        SIGNAL x_real      : bit_vector(15 downto 0);
        SIGNAL x_imag      : bit_vector(15 downto 0);
        SIGNAL y_real      : bit_vector(15 downto 0);
        SIGNAL y_imag      : bit_vector(15 downto 0);
        SIGNAL s_real      : bit_vector(15 downto 0);
        SIGNAL s_imag      : bit_vector(15 downto 0);
        SIGNAL ovf         : bit := '0';
                
BEGIN
        clk <= NOT clk AFTER 10 ns;
        clr <= '0' AFTER 20  ns, '1' AFTER 520 ns, '0' AFTER 560 ns, '1' AFTER 2980 ns, '0' AFTER 3020 ns;
        x_real <= "0100000000000000" AFTER 30 ns, "1100000000000000" AFTER 100 ns, "0000000000000000" AFTER 220 ns;
        x_imag <= "0100000000000000" AFTER 30 ns, "0010000000000000" AFTER 100 ns, "1000000000000000" AFTER 220 ns, "1010000000000000" AFTER 880 ns;
        y_real <= "0010000000000000" AFTER 30 ns, "0000000000000000" AFTER 100 ns;
        y_imag <= "0100000000000000" AFTER 30 ns, "0100000000000000" AFTER 100 ns, "0110000000000000" AFTER 220 ns, "1010000000000000" AFTER 240 ns, "0110000000000000" AFTER 440 ns;
        
        mac1: c_mac_gate PORT MAP (clk,clr,x_real,x_imag,y_real,y_imag,s_real,s_imag,ovf);
END tester;

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-- END of Test bench for Complex MAC
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