VHDL Source Code of Special Counter
at Structural Level(Gate level)
--------------------------------
-- VHDL code for Full Adder
--------------------------------
--##############################
--#Library of Full Adder
--##############################
--##############################
--#Entity of Full Adder
--##############################
ENTITY fullAdder IS
PORT (
x, y, cin: IN bit; -- inputs
cout, sum: OUT bit); -- outputs
END fullAdder;
--####################################
--# Implementing using the Full adder
--####################################
ARCHITECTURE equations OF fullAdder IS
BEGIN
sum <= x XOR y XOR cin;
cout <= (x AND y) OR (x AND cin) OR (y AND cin);
END equations;
---------------------------------------
-- end of VHDL code for Full Adder
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for Adder9
--------------------------------
--##############################
--#Library of Adder9
--##############################
--##############################
--#Entity of Adder9
--##############################
ENTITY adder9 IS
PORT (a, b: IN bit_vector(8 DOWNTO 0); ci: IN bit; -- Inputs
s: OUT bit_vector(8 DOWNTO 0); co: OUT bit); -- Outputs
END adder9;
--################################
--# Implementing using the adder9
--################################
ARCHITECTURE structure of adder9 is
COMPONENT fullAdder
PORT (x, y, cin: IN bit; -- Inputs
cout, sum: OUT bit); -- Outputs
END COMPONENT;
SIGNAL c: bit_vector(8 downto 1);
BEGIN --instantiate four copies of the FullAdder
fa0: fullAdder PORT MAP (a(0), b(0), ci, c(1), s(0));
fa1: fullAdder PORT MAP (a(1), b(1), c(1), c(2), s(1));
fa2: fullAdder PORT MAP (a(2), b(2), c(2), c(3), s(2));
fa3: fullAdder PORT MAP (a(3), b(3), c(3), c(4), s(3));
fa4: fullAdder PORT MAP (a(4), b(4), c(4), c(5), s(4));
fa5: fullAdder PORT MAP (a(5), b(5), c(5), c(6), s(5));
fa6: fullAdder PORT MAP (a(6), b(6), c(6), c(7), s(6));
fa7: fullAdder PORT MAP (a(7), b(7), c(7), c(8), s(7));
fa8: fullAdder PORT MAP (a(8), b(8), c(8), co, s(8));
end structure;
---------------------------------------
-- end of VHDL code for Adder9
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-------------------------------
-- VHDL code for D_FF
-------------------------------
ENTITY d_ff IS
PORT (d, clk: IN bit; -- inputs
q: OUT bit; -- outputs
qn: OUT bit:='1'); -- outputs
END d_ff;
ARCHITECTURE v1 OF d_ff IS
BEGIN
PROCESS (clk)
BEGIN
IF clk = '1' THEN
q <= d ;
qn <= NOT d;
END IF;
END PROCESS;
END v1;
-------------------------------
-- End of VHDL code for D_FF
-------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
----------------------------------
-- VHDL code for three D_FFs
----------------------------------
ENTITY tri_d_ffs IS
PORT (d: IN bit_vector(2 DOWNTO 0); -- inputs
clk: IN bit; -- inputs
q: OUT bit_vector(2 DOWNTO 0); -- outputs
qn:OUT bit_vector(2 DOWNTO 0) := "111"); -- outputs
END tri_d_ffs;
ARCHITECTURE v1 OF tri_d_ffs IS
COMPONENT d_ff
PORT (d, clk: IN bit; -- inputs
q : OUT bit; -- ouputs
qn : OUT bit:='1'); -- outputs
END COMPONENT;
BEGIN
dff0: d_ff PORT MAP (d(0), clk, q(0), qn(0));
dff1: d_ff PORT MAP (d(1), clk, q(1), qn(1));
dff2: d_ff PORT MAP (d(2), clk, q(2), qn(2));
END v1;
-----------------------------------
-- End of VHDL code for three D_FFs
-----------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
----------------------------------
-- VHDL code for nine D_FFs
----------------------------------
ENTITY nine_d_ffs IS
PORT (d: IN bit_vector(8 DOWNTO 0); -- inputs
clk: IN bit; -- inputs
q: OUT bit_vector(8 DOWNTO 0); -- outputs
qn:OUT bit_vector(8 DOWNTO 0) := "111111111"); -- outputs
END nine_d_ffs;
ARCHITECTURE v1 OF nine_d_ffs IS
COMPONENT d_ff
PORT (d, clk: IN bit; -- inputs
q : OUT bit; -- ouputs
qn : OUT bit:='1'); -- outputs
END COMPONENT;
BEGIN
dff0: d_ff PORT MAP (d(0), clk, q(0), qn(0));
dff1: d_ff PORT MAP (d(1), clk, q(1), qn(1));
dff2: d_ff PORT MAP (d(2), clk, q(2), qn(2));
dff3: d_ff PORT MAP (d(3), clk, q(3), qn(3));
dff4: d_ff PORT MAP (d(4), clk, q(4), qn(4));
dff5: d_ff PORT MAP (d(5), clk, q(5), qn(5));
dff6: d_ff PORT MAP (d(6), clk, q(6), qn(6));
dff7: d_ff PORT MAP (d(7), clk, q(7), qn(7));
dff8: d_ff PORT MAP (d(8), clk, q(8), qn(8));
END v1;
-----------------------------------
-- End of VHDL code for nine D_FFs
-----------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
----------------------------------
-- VHDL code for Multiplexer
----------------------------------
ENTITY multiplexer IS
PORT (d0: IN bit; -- inputs
d1: IN bit; -- inputs
d2: IN bit; -- inputs
d3: IN bit; -- inputs
up: IN bit; -- input
down: IN bit; -- input
rstn: IN bit; -- input
q: OUT bit ); -- outputs
END multiplexer;
ARCHITECTURE v1 OF multiplexer IS
BEGIN
q <= (rstn AND d0 AND (NOT up) AND (NOT down))
OR (rstn AND d1 AND (NOT up) AND down )
OR (rstn AND d2 AND up AND (NOT down))
OR (rstn AND d3 AND up AND down ) ;
END v1;
-----------------------------------
-- End of VHDL code for Multiplexer
-----------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for controlCircuit
--------------------------------
--##############################
--#Entity of controlCircuit
--##############################
ENTITY controlCircuit IS
PORT (
rstn, up, down : IN bit; -- input
data : IN bit_vector(8 downto 0); -- input
count_ff : IN bit_vector(8 downto 0); -- input
add_num1 : OUT bit_vector(8 downto 0); -- output
add_num2 : OUT bit_vector(8 downto 0) -- output
);
END controlCircuit;
--####################################
--# Implementing of controlCircuit
--####################################
ARCHITECTURE v1 OF controlCircuit IS
COMPONENT multiplexer
PORT (d0: IN bit; -- inputs
d1: IN bit; -- inputs
d2: IN bit; -- inputs
d3: IN bit; -- inputs
up: IN bit; -- input
down: IN bit; -- input
rstn: IN bit; -- input
q: OUT bit ); -- outputs
END COMPONENT;
BEGIN
mux0: multiplexer PORT MAP ('0', count_ff(0), count_ff(0), count_ff(0), up, down, rstn, add_num1(0));
mux1: multiplexer PORT MAP ('0', count_ff(1), count_ff(1), count_ff(1), up, down, rstn, add_num1(1));
mux2: multiplexer PORT MAP ('0', count_ff(2), count_ff(2), count_ff(2), up, down, rstn, add_num1(2));
mux3: multiplexer PORT MAP ('0', count_ff(3), count_ff(3), count_ff(3), up, down, rstn, add_num1(3));
mux4: multiplexer PORT MAP ('0', count_ff(4), count_ff(4), count_ff(4), up, down, rstn, add_num1(4));
mux5: multiplexer PORT MAP ('0', count_ff(5), count_ff(5), count_ff(5), up, down, rstn, add_num1(5));
mux6: multiplexer PORT MAP ('0', count_ff(6), count_ff(6), count_ff(6), up, down, rstn, add_num1(6));
mux7: multiplexer PORT MAP ('0', count_ff(7), count_ff(7), count_ff(7), up, down, rstn, add_num1(7));
mux8: multiplexer PORT MAP ('0', count_ff(8), count_ff(8), count_ff(8), up, down, rstn, add_num1(8));
mux9 : multiplexer PORT MAP (data(0), '1', '1', '0', up, down, rstn, add_num2(0));
mux10: multiplexer PORT MAP (data(1), '1', '1', '0', up, down, rstn, add_num2(1));
mux11: multiplexer PORT MAP (data(2), '0', '0', '0', up, down, rstn, add_num2(2));
mux12: multiplexer PORT MAP (data(3), '1', '0', '0', up, down, rstn, add_num2(3));
mux13: multiplexer PORT MAP (data(4), '1', '0', '0', up, down, rstn, add_num2(4));
mux14: multiplexer PORT MAP (data(5), '1', '0', '0', up, down, rstn, add_num2(5));
mux15: multiplexer PORT MAP (data(6), '1', '0', '0', up, down, rstn, add_num2(6));
mux16: multiplexer PORT MAP (data(7), '1', '0', '0', up, down, rstn, add_num2(7));
mux17: multiplexer PORT MAP (data(8), '1', '0', '0', up, down, rstn, add_num2(8));
END v1;
---------------------------------------
-- end of VHDL code for controlCircuit
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for addCircuit
--------------------------------
--##############################
--#Entity of addCircuit
--##############################
ENTITY addCircuit IS
PORT (
clk : IN bit; -- Inputs
a, b: IN bit_vector(8 DOWNTO 0); ci: IN bit; -- Inputs
new_count: INOUT bit_vector(8 DOWNTO 0); -- Outputs
count_ff: OUT bit_vector(8 DOWNTO 0); co: OUT bit); -- Outputs
END addCircuit;
--####################################
--# Implementing of addCircuit
--####################################
ARCHITECTURE v1 OF addCircuit IS
COMPONENT adder9
PORT (a, b: IN bit_vector(8 DOWNTO 0); ci: IN bit; -- Inputs
s: OUT bit_vector(8 DOWNTO 0); co: OUT bit); -- Outputs
END COMPONENT;
COMPONENT nine_d_ffs
PORT (d: IN bit_vector(8 DOWNTO 0); -- inputs
clk: IN bit; -- inputs
q: OUT bit_vector(8 DOWNTO 0); -- outputs
qn:OUT bit_vector(8 DOWNTO 0) := "111111111"); -- outputs
END COMPONENT;
SIGNAL count_ffn : bit_vector(8 downto 0);
BEGIN
add1: adder9 PORT MAP (a, b, ci, new_count, co);
dff9s: nine_d_ffs PORT MAP (new_count, clk, count_ff, count_ffn);
END v1;
---------------------------------------
-- end of VHDL code for addCircuit
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-------------------------------------------------------------
-- VHDL code for pbcCircuit(parity, borrow_out and carry_out)
-------------------------------------------------------------
--##############################
--#Entity of pbcCircuit
--##############################
ENTITY pbcCircuit IS
PORT (
rstn, clk, up, down : IN bit; -- input
count_ff : IN bit_vector(8 downto 0); -- input
carry_out : OUT bit; -- output
borrow_out : OUT bit; -- output
parity : OUT bit); -- output
END pbcCircuit;
--####################################
--# Implementing of pbcCircuit
--####################################
ARCHITECTURE v1 OF pbcCircuit IS
PROCEDURE parity_generator(
count_ff: IN bit_vector(8 downto 0);
SIGNAL parity : OUT bit
) IS
VARIABLE var1: bit := '0';
BEGIN
var1 := '0';
loop1: FOR i IN 0 TO 8 LOOP
IF count_ff(i) = '1' THEN
var1 := NOT var1;
END IF;
END LOOP loop1;
parity <= var1;
END parity_generator;
COMPONENT multiplexer
PORT (d0: IN bit; -- inputs
d1: IN bit; -- inputs
d2: IN bit; -- inputs
d3: IN bit; -- inputs
up: IN bit; -- input
down: IN bit; -- input
rstn: IN bit; -- input
q: OUT bit ); -- outputs
END COMPONENT;
COMPONENT tri_d_ffs
PORT (d: IN bit_vector(2 DOWNTO 0); -- inputs
clk: IN bit; -- inputs
q: OUT bit_vector(2 DOWNTO 0); -- outputs
qn:OUT bit_vector(2 DOWNTO 0) := "111"); -- outputs
END COMPONENT;
SIGNAL new_borrow : bit;
SIGNAL new_carry : bit;
SIGNAL new_parity : bit;
SIGNAL tmp_sig1 : bit;
SIGNAL tmp_sig2 : bit;
SIGNAL tmp_sig3 : bit_vector(2 DOWNTO 0) := "111";
SIGNAL tmp_sig4 : bit_vector(2 DOWNTO 0) := "111";
SIGNAL tmp_sig5 : bit_vector(2 DOWNTO 0) := "111";
SIGNAL tmp_sig6 : bit;
SIGNAL tmp_sig7 : bit;
SIGNAL tmp_sig8 : bit;
SIGNAL tmp_sig9 : bit;
SIGNAL tmp_sig10 : bit;
SIGNAL tmp_sig11 : bit;
SIGNAL tmp_sig12 : bit;
SIGNAL tmp_sig13 : bit;
SIGNAL tmp_sig14 : bit;
BEGIN
tmp_sig1 <= count_ff(8) AND count_ff(7) AND count_ff(6) AND count_ff(5) AND count_ff(4) AND count_ff(3)
AND count_ff(2) AND (count_ff(1) OR count_ff(0));
mux0: multiplexer PORT MAP ('0', '0', tmp_sig1, '0', up, down, rstn, new_carry);
tmp_sig2 <= ( NOT count_ff(8) ) AND ( NOT count_ff(7) ) AND ( NOT count_ff(6) ) AND ( NOT count_ff(5) ) AND ( NOT count_ff(4) ) AND ( NOT count_ff(3) )
AND ( (NOT count_ff(2)) OR ( (NOT count_ff(1)) AND (NOT count_ff(0)) ) );
mux1: multiplexer PORT MAP ('0', tmp_sig2, '0', '0', up, down, rstn, new_borrow);
tmp_sig3 <= new_carry & new_borrow & '1';
dff3s: tri_d_ffs PORT MAP (tmp_sig3, clk, tmp_sig4, tmp_sig5);
carry_out <= tmp_sig4(2);
borrow_out <= tmp_sig4(1);
-- parity_generator(count_ff, parity);
-- generate the parity bit
tmp_sig6 <= count_ff(0);
tmp_sig7 <= (count_ff(1) AND (NOT tmp_sig6)) OR ((NOT count_ff(1)) AND tmp_sig6);
tmp_sig8 <= (count_ff(2) AND (NOT tmp_sig7)) OR ((NOT count_ff(2)) AND tmp_sig7);
tmp_sig9 <= (count_ff(3) AND (NOT tmp_sig8)) OR ((NOT count_ff(3)) AND tmp_sig8);
tmp_sig10 <= (count_ff(4) AND (NOT tmp_sig9)) OR ((NOT count_ff(4)) AND tmp_sig9);
tmp_sig11 <= (count_ff(5) AND (NOT tmp_sig10)) OR ((NOT count_ff(5)) AND tmp_sig10);
tmp_sig12 <= (count_ff(6) AND (NOT tmp_sig11)) OR ((NOT count_ff(6)) AND tmp_sig11);
tmp_sig13 <= (count_ff(7) AND (NOT tmp_sig12)) OR ((NOT count_ff(7)) AND tmp_sig12);
tmp_sig14 <= (count_ff(8) AND (NOT tmp_sig13)) OR ((NOT count_ff(8)) AND tmp_sig13);
parity <= tmp_sig14 AFTER 1 ns;
END v1;
--------------------------------------------------------------------
-- end of VHDL code for pbcCircuit(parity, borrow_out and carry_out)
--------------------------------------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for Special Counter
--------------------------------
--##############################
--#Library of Special Counter
--##############################
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--##############################
--#Entity of Special Counter
--##############################
ENTITY count9 IS
PORT (
rstn, clk, up, down : IN bit; -- input
data : IN bit_vector(8 downto 0); -- input
count_ff : INOUT bit_vector(8 downto 0); -- input&output
carry_out : OUT bit; -- output
borrow_out : OUT bit; -- output
parity : OUT bit); -- output
END count9;
--###########################################################
--# Implementing using the counter at the Gates
--###########################################################
ARCHITECTURE v1 OF count9 IS
COMPONENT addCircuit
PORT (
clk : IN bit; -- Inputs
a, b: IN bit_vector(8 DOWNTO 0); ci: IN bit; -- Inputs
new_count: INOUT bit_vector(8 DOWNTO 0); -- Outputs
count_ff: OUT bit_vector(8 DOWNTO 0); co: OUT bit); -- Outputs
END COMPONENT;
COMPONENT controlCircuit
PORT (
rstn, up, down : IN bit; -- input
data : IN bit_vector(8 downto 0); -- input
count_ff : IN bit_vector(8 downto 0); -- input
add_num1 : OUT bit_vector(8 downto 0); -- output
add_num2 : OUT bit_vector(8 downto 0) -- output
);
END COMPONENT;
COMPONENT pbcCircuit
PORT (
rstn, clk, up, down : IN bit; -- input
count_ff : IN bit_vector(8 downto 0); -- input
carry_out : OUT bit; -- output
borrow_out : OUT bit; -- output
parity : OUT bit); -- output
END COMPONENT;
SIGNAL adder_input1 : bit_vector(8 downto 0);
SIGNAL adder_input2 : bit_vector(8 downto 0);
SIGNAL new_count : bit_vector(8 downto 0);
SIGNAL tmp_bit : bit;
BEGIN
ctl1: controlCircuit PORT MAP (rstn, up, down, data, count_ff, adder_input1, adder_input2);
add1: addCircuit PORT MAP (clk, adder_input1, adder_input2, '0', new_count, count_ff, tmp_bit);
pbc1: pbcCircuit PORT MAP (rstn, clk, up, down, count_ff, carry_out, borrow_out, parity);
END v1;
---------------------------------------
-- end of VHDL code for Special Counter
---------------------------------------
Go back to
My Homepage