VHDL Source Code of Special Counter
at RTL(Register Transfer Level)
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-- VHDL code for Special Counter
--------------------------------
--##############################
--#Library of Special Counter
--##############################
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY bitlib;
USE bitlib.bit_pack.all;
--##############################
--#Entity of Special Counter
--##############################
ENTITY count9 IS
PORT (
rstn, clk, up, down : IN bit; -- input
data : IN bit_vector(8 downto 0); -- input
count_ff : INOUT bit_vector(8 downto 0); -- output
carry_out : OUT bit; -- output
borrow_out : OUT bit; -- output
parity : OUT bit); -- output
END count9;
--###########################################################
--# Implementing using the counter at the RTL
--###########################################################
ARCHITECTURE v1 OF count9 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1'; -- assume it changes state on rising edge
IF rstn = '0' THEN count_ff <= "000000000";
ELSIF up = '0' and down = '0' THEN count_ff <= data;
ELSIF up = '1' and down = '1' THEN count_ff <= count_ff;
ELSIF up = '1' and down = '0' THEN count_ff <= int2vec(vec2int(count_ff)+3,9);
ELSIF up = '0' and down = '1' THEN count_ff <= int2vec(vec2int(count_ff)+507,9); -- "-5" is equals to "+(2^9-1-5+1)"
END IF;
IF rstn = '0' THEN
carry_out <= '0';
borrow_out <= '0';
ELSIF up = '0' and down = '0' THEN
carry_out <= '0';
borrow_out <= '0';
ELSIF up = '1' and down = '1' THEN
carry_out <= '0';
borrow_out <= '0';
ELSIF up = '1' and down = '0' THEN
IF count_ff = "111111111" OR count_ff = "111111110" OR count_ff = "111111101" THEN
carry_out <= '1';
ELSE
carry_out <= '0';
END IF;
borrow_out <= '0';
ELSIF up = '0' and down = '1' THEN
carry_out <= '0';
IF count_ff = "000000000" OR count_ff = "000000001" OR count_ff = "000000010" OR count_ff = "000000011" OR count_ff = "000000100" THEN
borrow_out <= '1';
ELSE
borrow_out <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (count_ff) -- calculate the current parity check bit
VARIABLE var1: bit := '0';
BEGIN
var1 := '0';
loop1: FOR i IN 0 TO 8 LOOP
IF count_ff(i) = '1' THEN
var1 := NOT var1;
END IF;
END LOOP loop1;
parity <= var1;
END PROCESS;
END v1;
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-- end of VHDL code for Special Counter
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