VHDL Source Code of SR_latch

--------------------------------
-- VHDL code for SR_Latch
--------------------------------

--##############################
--#Entity of SR latch
--##############################
ENTITY sr_latch IS
PORT (
  s, r: IN BIT := '0';
  q: INOUT BIT );
END sr_latch;



--###########################################################
--# Implementing using conditional two logic gates
--###########################################################
ARCHITECTURE v1 OF sr_latch IS
  SIGNAL p: BIT := '1';
BEGIN
  p <= s NOR q;
  q <= p NOR r;
END v1; 



--###########################################################
--# Implementing using conditional assignment statement
--###########################################################
ARCHITECTURE v2 OF sr_latch IS
  SIGNAL p: BIT := '1';
  SIGNAL old_q: BIT := '0';
BEGIN

  PROCESS (p, old_q, s, r)

  BEGIN

    old_q <= NOT ( p OR r );
        
    IF s = '0' AND r = '0' THEN
       p <= NOT old_q;
       q <= old_q;
    ELSIF s = '0' AND r = '1' THEN
       p <= '1';
       q <= '0';
    ELSIF s = '1' AND r = '0' THEN
       p <= '0';
       q <= '1';
    END IF;

  END PROCESS;

END v2; 



--###########################################################
--# Implementing using conditional assignment statement
--###########################################################
ARCHITECTURE v2_behavior2 OF sr_latch IS
BEGIN

  PROCESS (s, r)
  BEGIN
        
    IF s = '0' AND r = '0' THEN
       q <= q;
    ELSIF s = '0' AND r = '1' THEN
       q <= '0';
    ELSIF s = '1' AND r = '0' THEN
       q <= '1';
    END IF;
    
  END PROCESS;
  
END v2_behavior2; 



--###########################################################
--# Implementing using characteristic equation
--###########################################################
ARCHITECTURE v3 OF sr_latch IS
  SIGNAL p: BIT := '1';
  SIGNAL old_q: BIT := '0';
BEGIN
  p <= NOT ( s OR old_q );
  old_q <= NOT ( p OR r );
  q <= s OR  ((NOT r) AND old_q );
END v3; 

--###########################################################
--#Implementing using characteristic equation
--###########################################################

ARCHITECTURE v3_behavior2 OF sr_latch IS
BEGIN
  q <= s OR  ((NOT r) AND q );
END v3_behavior2; 

--------------------------------
-- end of VHDL code for SR latch
--------------------------------

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