VHDL Source Code of Mac in Gate Level
--------------------------------
-- VHDL code for Full Adder
--------------------------------
--##############################
--#Library of Full Adder
--##############################
--##############################
--#Entity of Full Adder
--##############################
ENTITY fullAdder IS
PORT (
x, y, cin: IN bit; -- inputs
cout, sum: OUT bit); -- outputs
END fullAdder;
--####################################
--# Implementing using the Full adder
--####################################
ARCHITECTURE equations OF fullAdder IS
BEGIN
sum <= x XOR y XOR cin;
cout <= (x AND y) OR (x AND cin) OR (y AND cin);
END equations;
---------------------------------------
-- end of VHDL code for Full Adder
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for Adder32
--------------------------------
--##############################
--#Library of Adder32
--##############################
--##############################
--#Entity of Adder32
--##############################
ENTITY adder32 IS
PORT (a, b: IN bit_vector(31 DOWNTO 0); ci: IN bit; -- Inputs
s: OUT bit_vector(31 DOWNTO 0); co: OUT bit); -- Outputs
END adder32;
--################################
--# Implementing using the adder32
--################################
ARCHITECTURE structure of adder32 is
COMPONENT fullAdder
PORT (x, y, cin: IN bit; -- Inputs
cout, sum: OUT bit); -- Outputs
END COMPONENT;
SIGNAL c: bit_vector(31 downto 1);
BEGIN --instantiate four copies of the FullAdder
fa0 : fullAdder PORT MAP (a(0), b(0), ci, c(1), s(0));
fa1 : fullAdder PORT MAP (a(1), b(1), c(1), c(2), s(1));
fa2 : fullAdder PORT MAP (a(2), b(2), c(2), c(3), s(2));
fa3 : fullAdder PORT MAP (a(3), b(3), c(3), c(4), s(3));
fa4 : fullAdder PORT MAP (a(4), b(4), c(4), c(5), s(4));
fa5 : fullAdder PORT MAP (a(5), b(5), c(5), c(6), s(5));
fa6 : fullAdder PORT MAP (a(6), b(6), c(6), c(7), s(6));
fa7 : fullAdder PORT MAP (a(7), b(7), c(7), c(8), s(7));
fa8 : fullAdder PORT MAP (a(8), b(8), c(8), c(9), s(8));
fa9 : fullAdder PORT MAP (a(9), b(9), c(9), c(10), s(9));
fa10: fullAdder PORT MAP (a(10), b(10), c(10), c(11), s(10));
fa11: fullAdder PORT MAP (a(11), b(11), c(11), c(12), s(11));
fa12: fullAdder PORT MAP (a(12), b(12), c(12), c(13), s(12));
fa13: fullAdder PORT MAP (a(13), b(13), c(13), c(14), s(13));
fa14: fullAdder PORT MAP (a(14), b(14), c(14), c(15), s(14));
fa15: fullAdder PORT MAP (a(15), b(15), c(15), c(16), s(15));
fa16: fullAdder PORT MAP (a(16), b(16), c(16), c(17), s(16));
fa17: fullAdder PORT MAP (a(17), b(17), c(17), c(18), s(17));
fa18: fullAdder PORT MAP (a(18), b(18), c(18), c(19), s(18));
fa19: fullAdder PORT MAP (a(19), b(19), c(19), c(20), s(19));
fa20: fullAdder PORT MAP (a(20), b(20), c(20), c(21), s(20));
fa21: fullAdder PORT MAP (a(21), b(21), c(21), c(22), s(21));
fa22: fullAdder PORT MAP (a(22), b(22), c(22), c(23), s(22));
fa23: fullAdder PORT MAP (a(23), b(23), c(23), c(24), s(23));
fa24: fullAdder PORT MAP (a(24), b(24), c(24), c(25), s(24));
fa25: fullAdder PORT MAP (a(25), b(25), c(25), c(26), s(25));
fa26: fullAdder PORT MAP (a(26), b(26), c(26), c(27), s(26));
fa27: fullAdder PORT MAP (a(27), b(27), c(27), c(28), s(27));
fa28: fullAdder PORT MAP (a(28), b(28), c(28), c(29), s(28));
fa29: fullAdder PORT MAP (a(29), b(29), c(29), c(30), s(29));
fa30: fullAdder PORT MAP (a(30), b(30), c(30), c(31), s(30));
fa31: fullAdder PORT MAP (a(31), b(31), c(31), co, s(31));
end structure;
---------------------------------------
-- end of VHDL code for Adder32
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for Adder16
--------------------------------
--##############################
--#Library of Adder16
--##############################
--##############################
--#Entity of Adder16
--##############################
ENTITY adder16 IS
PORT (a, b: IN bit_vector(15 DOWNTO 0); ci: IN bit; -- Inputs
s: OUT bit_vector(15 DOWNTO 0); co: OUT bit); -- Outputs
END adder16;
--################################
--# Implementing using the adder16
--################################
ARCHITECTURE structure of adder16 is
COMPONENT fullAdder
PORT (x, y, cin: IN bit; -- Inputs
cout, sum: OUT bit); -- Outputs
END COMPONENT;
SIGNAL c: bit_vector(15 downto 1);
BEGIN --instantiate four copies of the FullAdder
fa0 : fullAdder PORT MAP (a(0), b(0), ci, c(1), s(0));
fa1 : fullAdder PORT MAP (a(1), b(1), c(1), c(2), s(1));
fa2 : fullAdder PORT MAP (a(2), b(2), c(2), c(3), s(2));
fa3 : fullAdder PORT MAP (a(3), b(3), c(3), c(4), s(3));
fa4 : fullAdder PORT MAP (a(4), b(4), c(4), c(5), s(4));
fa5 : fullAdder PORT MAP (a(5), b(5), c(5), c(6), s(5));
fa6 : fullAdder PORT MAP (a(6), b(6), c(6), c(7), s(6));
fa7 : fullAdder PORT MAP (a(7), b(7), c(7), c(8), s(7));
fa8 : fullAdder PORT MAP (a(8), b(8), c(8), c(9), s(8));
fa9 : fullAdder PORT MAP (a(9), b(9), c(9), c(10), s(9));
fa10: fullAdder PORT MAP (a(10), b(10), c(10), c(11), s(10));
fa11: fullAdder PORT MAP (a(11), b(11), c(11), c(12), s(11));
fa12: fullAdder PORT MAP (a(12), b(12), c(12), c(13), s(12));
fa13: fullAdder PORT MAP (a(13), b(13), c(13), c(14), s(13));
fa14: fullAdder PORT MAP (a(14), b(14), c(14), c(15), s(14));
fa15: fullAdder PORT MAP (a(15), b(15), c(15), co, s(15));
end structure;
---------------------------------------
-- end of VHDL code for Adder20
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-------------------------------
-- VHDL code for D_FF
-------------------------------
ENTITY d_ff IS
PORT (d, clk: IN bit; -- inputs
clr : IN bit; -- inputs
q: OUT bit; -- outputs
qn: OUT bit:='1'); -- outputs
END d_ff;
ARCHITECTURE v1 OF d_ff IS
BEGIN
PROCESS (clk, clr)
BEGIN
IF clr = '1' THEN
q <= '0';
ELSIF (clk'event) AND (clk = '1') THEN
q <= d ;
END IF;
END PROCESS;
qn <= NOT d;
END v1;
-------------------------------
-- End of VHDL code for D_FF
-------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
----------------------------------
-- VHDL code for D_FF32s
----------------------------------
ENTITY d_ff32s IS
PORT (d: IN bit_vector(31 DOWNTO 0); -- inputs
clk: IN bit; -- inputs
clr : IN bit; -- inputs
q: OUT bit_vector(31 DOWNTO 0); -- outputs
qn:OUT bit_vector(31 DOWNTO 0) := "11111111111111111111111111111111"); -- outputs
END d_ff32s;
ARCHITECTURE v1 OF d_ff32s IS
COMPONENT d_ff
PORT (d, clk: IN bit; -- inputs
clr : IN bit; -- inputs
q : OUT bit; -- ouputs
qn : OUT bit:='1'); -- outputs
END COMPONENT;
BEGIN
dff0: d_ff PORT MAP (d(0), clk, clr, q(0), qn(0));
dff1: d_ff PORT MAP (d(1), clk, clr, q(1), qn(1));
dff2: d_ff PORT MAP (d(2), clk, clr, q(2), qn(2));
dff3: d_ff PORT MAP (d(3), clk, clr, q(3), qn(3));
dff4: d_ff PORT MAP (d(4), clk, clr, q(4), qn(4));
dff5: d_ff PORT MAP (d(5), clk, clr, q(5), qn(5));
dff6: d_ff PORT MAP (d(6), clk, clr, q(6), qn(6));
dff7: d_ff PORT MAP (d(7), clk, clr, q(7), qn(7));
dff8: d_ff PORT MAP (d(8), clk, clr, q(8), qn(8));
dff9: d_ff PORT MAP (d(9), clk, clr, q(9), qn(9));
dff10: d_ff PORT MAP (d(10), clk, clr, q(10), qn(10));
dff11: d_ff PORT MAP (d(11), clk, clr, q(11), qn(11));
dff12: d_ff PORT MAP (d(12), clk, clr, q(12), qn(12));
dff13: d_ff PORT MAP (d(13), clk, clr, q(13), qn(13));
dff14: d_ff PORT MAP (d(14), clk, clr, q(14), qn(14));
dff15: d_ff PORT MAP (d(15), clk, clr, q(15), qn(15));
dff16: d_ff PORT MAP (d(16), clk, clr, q(16), qn(16));
dff17: d_ff PORT MAP (d(17), clk, clr, q(17), qn(17));
dff18: d_ff PORT MAP (d(18), clk, clr, q(18), qn(18));
dff19: d_ff PORT MAP (d(19), clk, clr, q(19), qn(19));
dff20: d_ff PORT MAP (d(20), clk, clr, q(20), qn(20));
dff21: d_ff PORT MAP (d(21), clk, clr, q(21), qn(21));
dff22: d_ff PORT MAP (d(22), clk, clr, q(22), qn(22));
dff23: d_ff PORT MAP (d(23), clk, clr, q(23), qn(23));
dff24: d_ff PORT MAP (d(24), clk, clr, q(24), qn(24));
dff25: d_ff PORT MAP (d(25), clk, clr, q(25), qn(25));
dff26: d_ff PORT MAP (d(26), clk, clr, q(26), qn(26));
dff27: d_ff PORT MAP (d(27), clk, clr, q(27), qn(27));
dff28: d_ff PORT MAP (d(28), clk, clr, q(28), qn(28));
dff29: d_ff PORT MAP (d(29), clk, clr, q(29), qn(29));
dff30: d_ff PORT MAP (d(30), clk, clr, q(30), qn(30));
dff31: d_ff PORT MAP (d(31), clk, clr, q(31), qn(31));
END v1;
-----------------------------------
-- End of VHDL code for D_FF32s
-----------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for inverter16
--------------------------------
ENTITY inverter16 IS
PORT (a: IN bit_vector(15 DOWNTO 0); -- inputs
z: OUT bit_vector(15 DOWNTO 0) ); -- outputs
END inverter16;
ARCHITECTURE v1 OF inverter16 IS
BEGIN
z(0) <= NOT a(0);
z(1) <= NOT a(1);
z(2) <= NOT a(2);
z(3) <= NOT a(3);
z(4) <= NOT a(4);
z(5) <= NOT a(5);
z(6) <= NOT a(6);
z(7) <= NOT a(7);
z(8) <= NOT a(8);
z(9) <= NOT a(9);
z(10) <= NOT a(10);
z(11) <= NOT a(11);
z(12) <= NOT a(12);
z(13) <= NOT a(13);
z(14) <= NOT a(14);
z(15) <= NOT a(15);
END v1;
-----------------------------------
-- End of VHDL code for inverter16
-----------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for 2's complement
-- (16 bits)
--------------------------------
--##############################
--#Entity of two_s_complement16
--##############################
ENTITY two_s_complement16 IS
PORT (
a: IN bit_vector(15 DOWNTO 0); -- Inputs
z: OUT bit_vector(15 DOWNTO 0) ); -- Outputs
END two_s_complement16;
--####################################
--# Implementing of two_s_complement16
--####################################
ARCHITECTURE v1 OF two_s_complement16 IS
COMPONENT adder16
PORT (a, b: IN bit_vector(15 DOWNTO 0); ci: IN bit; -- Inputs
s: OUT bit_vector(15 DOWNTO 0); co: OUT bit); -- Outputs
END COMPONENT;
COMPONENT inverter16
PORT (a: IN bit_vector(15 DOWNTO 0); -- inputs
z: OUT bit_vector(15 DOWNTO 0) ); -- outputs
END COMPONENT;
SIGNAL tmp_vec : bit_vector(15 downto 0);
BEGIN
inverter: inverter16 PORT MAP (a, tmp_vec);
adder: adder16 PORT MAP ("0000000000000000", tmp_vec, '1', z);
END v1;
------------------------------------------
-- end of VHDL code for two_s_complement16
------------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for 2's complement
-- (32 bits)
--------------------------------
--##############################
--#Entity of two_s_complement32
--##############################
ENTITY two_s_complement32 IS
PORT (
a: IN bit_vector(31 DOWNTO 0); -- Inputs
z: OUT bit_vector(31 DOWNTO 0) ); -- Outputs
END two_s_complement32;
--####################################
--# Implementing of two_s_complement32
--####################################
ARCHITECTURE v1 OF two_s_complement32 IS
COMPONENT adder32
PORT (a, b: IN bit_vector(31 DOWNTO 0); ci: IN bit; -- Inputs
s: OUT bit_vector(31 DOWNTO 0); co: OUT bit); -- Outputs
END COMPONENT;
COMPONENT inverter16
PORT (a: IN bit_vector(15 DOWNTO 0); -- inputs
z: OUT bit_vector(15 DOWNTO 0) ); -- outputs
END COMPONENT;
SIGNAL tmp_vec : bit_vector(31 downto 0);
BEGIN
inverter1: inverter16 PORT MAP (a(15 downto 0 ), tmp_vec(15 downto 0));
inverter2: inverter16 PORT MAP (a(31 downto 16), tmp_vec(31 downto 16));
adder32_1: adder32 PORT MAP ("00000000000000000000000000000000", tmp_vec, '1', z);
END v1;
------------------------------------------
-- end of VHDL code for two_s_complement16
------------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for expanding range
-- From [-1, 1] to [-16, 16]
--------------------------------
--##############################
--#Entity of expanding_range
--##############################
ENTITY expanding_range IS
PORT (
a: IN bit_vector(31 DOWNTO 0); -- Inputs
z: OUT bit_vector(31 DOWNTO 0) ); -- Outputs
END expanding_range;
--####################################
--# Implementing of expanding_range
--####################################
ARCHITECTURE v1 OF expanding_range IS
BEGIN
z(0) <= a(3);
z(1) <= a(4);
z(2) <= a(5);
z(3) <= a(6);
z(4) <= a(7);
z(5) <= a(8);
z(6) <= a(9);
z(7) <= a(10);
z(8) <= a(11);
z(9) <= a(12);
z(10) <= a(13);
z(11) <= a(14);
z(12) <= a(15);
z(13) <= a(16);
z(14) <= a(17);
z(15) <= a(18);
z(16) <= a(19);
z(17) <= a(20);
z(18) <= a(21);
z(19) <= a(22);
z(20) <= a(23);
z(21) <= a(24);
z(22) <= a(25);
z(23) <= a(26);
z(24) <= a(27);
z(25) <= a(28);
z(26) <= a(29);
z(27) <= a(30);
z(28) <= a(30);
z(29) <= a(30);
z(30) <= a(30);
z(31) <= a(30);
END v1;
------------------------------------------
-- end of VHDL code for expanding_range
------------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for D_Latch
--------------------------------
--####################################
--#Entity of D latch with "clr" signal
--####################################
ENTITY d_latch IS
PORT (
g, d, clr: IN BIT := '0';
q: INOUT BIT := '0');
END d_latch;
--#######################################
--# Implementing using characteristic
--# equations
--# Note: when clr = '1', then q+ <= '0'
--#######################################
ARCHITECTURE v1 OF d_latch IS
BEGIN
q <= (NOT clr) AND ((g AND d) OR ((NOT g) AND q));
END v1;
--------------------------------
-- end of VHDL code for D latch
--------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for ovf circuit
--------------------------------
--##############################
--#Entity of ovf circuit
--##############################
ENTITY ovfCircuit IS
PORT (
acc_ovf: IN bit; -- input
sum_ovf: IN bit; -- input
clr: IN bit; -- input
ovf: OUT bit); -- output
END ovfCircuit;
--##############################
--#Implementation of ovf circuit
--##############################
ARCHITECTURE v1 OF ovfCircuit IS
COMPONENT d_latch
PORT (
g, d, clr: IN BIT := '0';
q: INOUT BIT := '0');
END COMPONENT;
SIGNAL latched_sum_ovf: bit;
SIGNAL tmp_ovf: bit;
BEGIN
d_latch1: d_latch PORT MAP(sum_ovf, '1', clr, latched_sum_ovf);
ovf <= latched_sum_ovf OR acc_ovf;
END v1;
-----------------------------------
-- end of VHDL code for ovf circuit
-----------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
----------------------------------
-- VHDL code for Multiplexer
----------------------------------
ENTITY multiplexer2 IS
PORT (d0: IN bit; -- input
d1: IN bit; -- input
sel: IN bit; -- input
q: OUT bit ); -- outputs
END multiplexer2;
ARCHITECTURE v1 OF multiplexer2 IS
BEGIN
q <= ( d0 AND (NOT sel) )
OR ( d1 AND sel ) ;
END v1;
-----------------------------------
-- End of VHDL code for Multiplexer
-----------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
----------------------------------
-- VHDL code for data_preprocess16
--======================
-- If a negative number,
-- get its 2's complement;
-- or else, do nothing.
----------------------------------
ENTITY data_preprocess16 IS
PORT (d: IN bit_vector(15 downto 0); -- input
sign: IN bit; -- input <the sign bit: used for selecting 2's complement or not
q: OUT bit_vector(15 downto 0)); -- outputs
END data_preprocess16;
ARCHITECTURE v1 OF data_preprocess16 IS
COMPONENT two_s_complement16
PORT (
a: IN bit_vector(15 downto 0); -- Inputs
z: OUT bit_vector(15 downto 0) ); -- Outputs
END COMPONENT;
COMPONENT multiplexer2
PORT (d0 : IN bit; -- input
d1 : IN bit; -- input
sel: IN bit; -- input
q : OUT bit ); -- outputs
END COMPONENT;
SIGNAL tmp_vec: bit_vector(15 downto 0);
BEGIN
two_complement: two_s_complement16 PORT MAP (d, tmp_vec);
mux0: multiplexer2 PORT MAP (d(0), tmp_vec(0), sign, q(0));
mux1: multiplexer2 PORT MAP (d(1), tmp_vec(1), sign, q(1));
mux2: multiplexer2 PORT MAP (d(2), tmp_vec(2), sign, q(2));
mux3: multiplexer2 PORT MAP (d(3), tmp_vec(3), sign, q(3));
mux4: multiplexer2 PORT MAP (d(4), tmp_vec(4), sign, q(4));
mux5: multiplexer2 PORT MAP (d(5), tmp_vec(5), sign, q(5));
mux6: multiplexer2 PORT MAP (d(6), tmp_vec(6), sign, q(6));
mux7: multiplexer2 PORT MAP (d(7), tmp_vec(7), sign, q(7));
mux8: multiplexer2 PORT MAP (d(8), tmp_vec(8), sign, q(8));
mux9: multiplexer2 PORT MAP (d(9), tmp_vec(9), sign, q(9));
mux10: multiplexer2 PORT MAP (d(10), tmp_vec(10), sign, q(10));
mux11: multiplexer2 PORT MAP (d(11), tmp_vec(11), sign, q(11));
mux12: multiplexer2 PORT MAP (d(12), tmp_vec(12), sign, q(12));
mux13: multiplexer2 PORT MAP (d(13), tmp_vec(13), sign, q(13));
mux14: multiplexer2 PORT MAP (d(14), tmp_vec(14), sign, q(14));
mux15: multiplexer2 PORT MAP (d(15), tmp_vec(15), sign, q(15));
END v1;
---------------------------------------
-- End of VHDL code for data_preprocess16
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
----------------------------------
-- VHDL code for data_preprocess32
--======================
-- If a negative number,
-- get its 2's complement;
-- or else, do nothing.
----------------------------------
ENTITY data_preprocess32 IS
PORT (d: IN bit_vector(31 downto 0); -- input
sign: IN bit; -- input <the sign bit: used for selecting 2's complement or not
q: OUT bit_vector(31 downto 0)); -- outputs
END data_preprocess32;
ARCHITECTURE v1 OF data_preprocess32 IS
COMPONENT two_s_complement32
PORT (
a: IN bit_vector(31 downto 0); -- Inputs
z: OUT bit_vector(31 downto 0) ); -- Outputs
END COMPONENT;
COMPONENT multiplexer2
PORT (d0 : IN bit; -- input
d1 : IN bit; -- input
sel: IN bit; -- input
q : OUT bit ); -- outputs
END COMPONENT;
SIGNAL tmp_vec: bit_vector(31 downto 0);
BEGIN
two_complement: two_s_complement32 PORT MAP (d, tmp_vec);
mux0: multiplexer2 PORT MAP (d(0), tmp_vec(0), sign, q(0));
mux1: multiplexer2 PORT MAP (d(1), tmp_vec(1), sign, q(1));
mux2: multiplexer2 PORT MAP (d(2), tmp_vec(2), sign, q(2));
mux3: multiplexer2 PORT MAP (d(3), tmp_vec(3), sign, q(3));
mux4: multiplexer2 PORT MAP (d(4), tmp_vec(4), sign, q(4));
mux5: multiplexer2 PORT MAP (d(5), tmp_vec(5), sign, q(5));
mux6: multiplexer2 PORT MAP (d(6), tmp_vec(6), sign, q(6));
mux7: multiplexer2 PORT MAP (d(7), tmp_vec(7), sign, q(7));
mux8: multiplexer2 PORT MAP (d(8), tmp_vec(8), sign, q(8));
mux9: multiplexer2 PORT MAP (d(9), tmp_vec(9), sign, q(9));
mux10: multiplexer2 PORT MAP (d(10), tmp_vec(10), sign, q(10));
mux11: multiplexer2 PORT MAP (d(11), tmp_vec(11), sign, q(11));
mux12: multiplexer2 PORT MAP (d(12), tmp_vec(12), sign, q(12));
mux13: multiplexer2 PORT MAP (d(13), tmp_vec(13), sign, q(13));
mux14: multiplexer2 PORT MAP (d(14), tmp_vec(14), sign, q(14));
mux15: multiplexer2 PORT MAP (d(15), tmp_vec(15), sign, q(15));
mux16: multiplexer2 PORT MAP (d(16), tmp_vec(16), sign, q(16));
mux17: multiplexer2 PORT MAP (d(17), tmp_vec(17), sign, q(17));
mux18: multiplexer2 PORT MAP (d(18), tmp_vec(18), sign, q(18));
mux19: multiplexer2 PORT MAP (d(19), tmp_vec(19), sign, q(19));
mux20: multiplexer2 PORT MAP (d(20), tmp_vec(20), sign, q(20));
mux21: multiplexer2 PORT MAP (d(21), tmp_vec(21), sign, q(21));
mux22: multiplexer2 PORT MAP (d(22), tmp_vec(22), sign, q(22));
mux23: multiplexer2 PORT MAP (d(23), tmp_vec(23), sign, q(23));
mux24: multiplexer2 PORT MAP (d(24), tmp_vec(24), sign, q(24));
mux25: multiplexer2 PORT MAP (d(25), tmp_vec(25), sign, q(25));
mux26: multiplexer2 PORT MAP (d(26), tmp_vec(26), sign, q(26));
mux27: multiplexer2 PORT MAP (d(27), tmp_vec(27), sign, q(27));
mux28: multiplexer2 PORT MAP (d(28), tmp_vec(28), sign, q(28));
mux29: multiplexer2 PORT MAP (d(29), tmp_vec(29), sign, q(29));
mux30: multiplexer2 PORT MAP (d(30), tmp_vec(30), sign, q(30));
mux31: multiplexer2 PORT MAP (d(31), tmp_vec(31), sign, q(31));
END v1;
---------------------------------------
-- End of VHDL code for data_preprocess32
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
----------------------------------
-- VHDL code for mutl16X16 circuit
----------------------------------
--##############################
--#Entity of mutl16X16 circuit
--##############################
ENTITY mutl16X16Circuit IS
PORT (
--mcand, mplier : IN bit_vector(15 downto 0);
x, y : IN bit_vector(15 downto 0); -- inputs
--product: OUT bit_vector(31 downto 0)
p: OUT bit_vector(31 downto 0) -- outputs
);
END mutl16X16Circuit;
--####################################
--#Implementation of mutl16X16 circuit
--#Using AND gates and adders array
--####################################
ARCHITECTURE v1 OF mutl16X16Circuit IS
COMPONENT fullAdder
PORT (x, y, cin: IN bit; -- Inputs
cout, sum: OUT bit); -- Outputs
END COMPONENT;
TYPE Matrix16x16 IS array (0 to 15, 0 to 15) of bit;
SIGNAL c: Matrix16x16; -- carry out bits
SIGNAL s: Matrix16x16; -- sum bits
SIGNAL tmp_bit1: bit ;
SIGNAL x_tmp : Matrix16x16;
SIGNAL y_tmp : Matrix16x16;
BEGIN
-- row 0, 1
s(0,0) <= x(0) AND y(0);
p(0) <= s(0,0);
x_tmp(1,0) <= x(1) AND y(0);
y_tmp(0,1) <= x(0) AND y(1);
fa1_0: fullAdder PORT MAP (x_tmp(1,0), y_tmp(0,1), '0', c(1,0), s(1,0));
p(1) <= s(1,0);
x_tmp(2,0) <= x(2) AND y(0);
y_tmp(1,1) <= x(1) AND y(1);
fa1_1: fullAdder PORT MAP (x_tmp(2,0), y_tmp(1,1), c(1,0), c(1,1), s(1,1));
x_tmp(3,0) <= x(3) AND y(0);
y_tmp(2,1) <= x(2) AND y(1);
fa1_2: fullAdder PORT MAP (x_tmp(3,0), y_tmp(2,1), c(1,1), c(1,2), s(1,2));
x_tmp(4,0) <= x(4) AND y(0);
y_tmp(3,1) <= x(3) AND y(1);
fa1_3: fullAdder PORT MAP (x_tmp(4,0), y_tmp(3,1), c(1,2), c(1,3), s(1,3));
x_tmp(5,0) <= x(5) AND y(0);
y_tmp(4,1) <= x(4) AND y(1);
fa1_4: fullAdder PORT MAP (x_tmp(5,0), y_tmp(4,1), c(1,3), c(1,4), s(1,4));
x_tmp(6,0) <= x(6) AND y(0);
y_tmp(5,1) <= x(5) AND y(1);
fa1_5: fullAdder PORT MAP (x_tmp(6,0), y_tmp(5,1), c(1,4), c(1,5), s(1,5));
x_tmp(7,0) <= x(7) AND y(0);
y_tmp(6,1) <= x(6) AND y(1);
fa1_6: fullAdder PORT MAP (x_tmp(7,0), y_tmp(6,1), c(1,5), c(1,6), s(1,6));
x_tmp(8,0) <= x(8) AND y(0);
y_tmp(7,1) <= x(7) AND y(1);
fa1_7: fullAdder PORT MAP (x_tmp(8,0), y_tmp(7,1), c(1,6), c(1,7), s(1,7));
x_tmp(9,0) <= x(9) AND y(0);
y_tmp(8,1) <= x(8) AND y(1);
fa1_8: fullAdder PORT MAP (x_tmp(9,0), y_tmp(8,1), c(1,7), c(1,8), s(1,8));
x_tmp(10,0) <= x(10) AND y(0);
y_tmp(9,1) <= x(9) AND y(1);
fa1_9: fullAdder PORT MAP (x_tmp(10,0), y_tmp(9,1), c(1,8), c(1,9), s(1,9));
x_tmp(11,0) <= x(11) AND y(0);
y_tmp(10,1) <= x(10) AND y(1);
fa1_10: fullAdder PORT MAP (x_tmp(11,0), y_tmp(10,1), c(1,9), c(1,10), s(1,10));
x_tmp(12,0) <= x(12) AND y(0);
y_tmp(11,1) <= x(11) AND y(1);
fa1_11: fullAdder PORT MAP (x_tmp(12,0), y_tmp(11,1), c(1,10), c(1,11), s(1,11));
x_tmp(13,0) <= x(13) AND y(0);
y_tmp(12,1) <= x(12) AND y(1);
fa1_12: fullAdder PORT MAP (x_tmp(13,0), y_tmp(12,1), c(1,11), c(1,12), s(1,12));
x_tmp(14,0) <= x(14) AND y(0);
y_tmp(13,1) <= x(13) AND y(1);
fa1_13: fullAdder PORT MAP (x_tmp(14,0), y_tmp(13,1), c(1,12), c(1,13), s(1,13));
x_tmp(15,0) <= x(15) AND y(0);
y_tmp(14,1) <= x(14) AND y(1);
fa1_14: fullAdder PORT MAP (x_tmp(15,0), y_tmp(14,1), c(1,13), c(1,14), s(1,14));
y_tmp(15,1) <= x(15) AND y(1);
fa1_15: fullAdder PORT MAP ('0', y_tmp(15,1), c(1,14), c(1,15), s(1,15));
-- row 2
y_tmp(0,2) <= x(0) AND y(2);
fa2_0: fullAdder PORT MAP (s(1,1), y_tmp(0,2), '0', c(2,0), s(2,0));
p(2) <= s(2,0);
y_tmp(1,2) <= x(1) AND y(2);
fa2_1: fullAdder PORT MAP (s(1,2), y_tmp(1,2), c(2,0), c(2,1), s(2,1));
y_tmp(2,2) <= x(2) AND y(2);
fa2_2: fullAdder PORT MAP (s(1,3), y_tmp(2,2), c(2,1), c(2,2), s(2,2));
y_tmp(3,2) <= x(3) AND y(2);
fa2_3: fullAdder PORT MAP (s(1,4), y_tmp(3,2), c(2,2), c(2,3), s(2,3));
y_tmp(4,2) <= x(4) AND y(2);
fa2_4: fullAdder PORT MAP (s(1,5), y_tmp(4,2), c(2,3), c(2,4), s(2,4));
y_tmp(5,2) <= x(5) AND y(2);
fa2_5: fullAdder PORT MAP (s(1,6), y_tmp(5,2), c(2,4), c(2,5), s(2,5));
y_tmp(6,2) <= x(6) AND y(2);
fa2_6: fullAdder PORT MAP (s(1,7), y_tmp(6,2), c(2,5), c(2,6), s(2,6));
y_tmp(7,2) <= x(7) AND y(2);
fa2_7: fullAdder PORT MAP (s(1,8), y_tmp(7,2), c(2,6), c(2,7), s(2,7));
y_tmp(8,2) <= x(8) AND y(2);
fa2_8: fullAdder PORT MAP (s(1,9), y_tmp(8,2), c(2,7), c(2,8), s(2,8));
y_tmp(9,2) <= x(9) AND y(2);
fa2_9: fullAdder PORT MAP (s(1,10), y_tmp(9,2), c(2,8), c(2,9), s(2,9));
y_tmp(10,2) <= x(10) AND y(2);
fa2_10: fullAdder PORT MAP (s(1,11), y_tmp(10,2), c(2,9), c(2,10), s(2,10));
y_tmp(11,2) <= x(11) AND y(2);
fa2_11: fullAdder PORT MAP (s(1,12), y_tmp(11,2), c(2,10), c(2,11), s(2,11));
y_tmp(12,2) <= x(12) AND y(2);
fa2_12: fullAdder PORT MAP (s(1,13), y_tmp(12,2), c(2,11), c(2,12), s(2,12));
y_tmp(13,2) <= x(13) AND y(2);
fa2_13: fullAdder PORT MAP (s(1,14), y_tmp(13,2), c(2,12), c(2,13), s(2,13));
y_tmp(14,2) <= x(14) AND y(2);
fa2_14: fullAdder PORT MAP (s(1,15), y_tmp(14,2), c(2,13), c(2,14), s(2,14));
y_tmp(15,2) <= x(15) AND y(2);
fa2_15: fullAdder PORT MAP (c(1,15), y_tmp(15,2), c(2,14), c(2,15), s(2,15));
-- row 3
y_tmp(0,3) <= x(0) AND y(3);
fa3_0: fullAdder PORT MAP (s(2,1), y_tmp(0,3), '0', c(3,0), s(3,0));
p(3) <= s(3,0);
y_tmp(1,3) <= x(1) AND y(3);
fa3_1: fullAdder PORT MAP (s(2,2), y_tmp(1,3), c(3,0), c(3,1), s(3,1));
y_tmp(2,3) <= x(2) AND y(3);
fa3_2: fullAdder PORT MAP (s(2,3), y_tmp(2,3), c(3,1), c(3,2), s(3,2));
y_tmp(3,3) <= x(3) AND y(3);
fa3_3: fullAdder PORT MAP (s(2,4), y_tmp(3,3), c(3,2), c(3,3), s(3,3));
y_tmp(4,3) <= x(4) AND y(3);
fa3_4: fullAdder PORT MAP (s(2,5), y_tmp(4,3), c(3,3), c(3,4), s(3,4));
y_tmp(5,3) <= x(5) AND y(3);
fa3_5: fullAdder PORT MAP (s(2,6), y_tmp(5,3), c(3,4), c(3,5), s(3,5));
y_tmp(6,3) <= x(6) AND y(3);
fa3_6: fullAdder PORT MAP (s(2,7), y_tmp(6,3), c(3,5), c(3,6), s(3,6));
y_tmp(7,3) <= x(7) AND y(3);
fa3_7: fullAdder PORT MAP (s(2,8), y_tmp(7,3), c(3,6), c(3,7), s(3,7));
y_tmp(8,3) <= x(8) AND y(3);
fa3_8: fullAdder PORT MAP (s(2,9), y_tmp(8,3), c(3,7), c(3,8), s(3,8));
y_tmp(9,3) <= x(9) AND y(3);
fa3_9: fullAdder PORT MAP (s(2,10), y_tmp(9,3), c(3,8), c(3,9), s(3,9));
y_tmp(10,3) <= x(10) AND y(3);
fa3_10: fullAdder PORT MAP (s(2,11), y_tmp(10,3), c(3,9), c(3,10), s(3,10));
y_tmp(11,3) <= x(11) AND y(3);
fa3_11: fullAdder PORT MAP (s(2,12), y_tmp(11,3), c(3,10), c(3,11), s(3,11));
y_tmp(12,3) <= x(12) AND y(3);
fa3_12: fullAdder PORT MAP (s(2,13), y_tmp(12,3), c(3,11), c(3,12), s(3,12));
y_tmp(13,3) <= x(13) AND y(3);
fa3_13: fullAdder PORT MAP (s(2,14), y_tmp(13,3), c(3,12), c(3,13), s(3,13));
y_tmp(14,3) <= x(14) AND y(3);
fa3_14: fullAdder PORT MAP (s(2,15), y_tmp(14,3), c(3,13), c(3,14), s(3,14));
y_tmp(15,3) <= x(15) AND y(3);
fa3_15: fullAdder PORT MAP (c(2,15), y_tmp(15,3), c(3,14), c(3,15), s(3,15));
-- row 4
y_tmp(0,4) <= x(0) AND y(4);
fa4_0: fullAdder PORT MAP (s(3,1), y_tmp(0,4), '0', c(4,0), s(4,0));
p(4) <= s(4,0);
y_tmp(1,4) <= x(1) AND y(4);
fa4_1: fullAdder PORT MAP (s(3,2), y_tmp(1,4), c(4,0), c(4,1), s(4,1));
y_tmp(2,4) <= x(2) AND y(4);
fa4_2: fullAdder PORT MAP (s(3,3), y_tmp(2,4), c(4,1), c(4,2), s(4,2));
y_tmp(3,4) <= x(3) AND y(4);
fa4_3: fullAdder PORT MAP (s(3,4), y_tmp(3,4), c(4,2), c(4,3), s(4,3));
y_tmp(4,4) <= x(4) AND y(4);
fa4_4: fullAdder PORT MAP (s(3,5), y_tmp(4,4), c(4,3), c(4,4), s(4,4));
y_tmp(5,4) <= x(5) AND y(4);
fa4_5: fullAdder PORT MAP (s(3,6), y_tmp(5,4), c(4,4), c(4,5), s(4,5));
y_tmp(6,4) <= x(6) AND y(4);
fa4_6: fullAdder PORT MAP (s(3,7), y_tmp(6,4), c(4,5), c(4,6), s(4,6));
y_tmp(7,4) <= x(7) AND y(4);
fa4_7: fullAdder PORT MAP (s(3,8), y_tmp(7,4), c(4,6), c(4,7), s(4,7));
y_tmp(8,4) <= x(8) AND y(4);
fa4_8: fullAdder PORT MAP (s(3,9), y_tmp(8,4), c(4,7), c(4,8), s(4,8));
y_tmp(9,4) <= x(9) AND y(4);
fa4_9: fullAdder PORT MAP (s(3,10), y_tmp(9,4), c(4,8), c(4,9), s(4,9));
y_tmp(10,4) <= x(10) AND y(4);
fa4_10: fullAdder PORT MAP (s(3,11), y_tmp(10,4), c(4,9), c(4,10), s(4,10));
y_tmp(11,4) <= x(11) AND y(4);
fa4_11: fullAdder PORT MAP (s(3,12), y_tmp(11,4), c(4,10), c(4,11), s(4,11));
y_tmp(12,4) <= x(12) AND y(4);
fa4_12: fullAdder PORT MAP (s(3,13), y_tmp(12,4), c(4,11), c(4,12), s(4,12));
y_tmp(13,4) <= x(13) AND y(4);
fa4_13: fullAdder PORT MAP (s(3,14), y_tmp(13,4), c(4,12), c(4,13), s(4,13));
y_tmp(14,4) <= x(14) AND y(4);
fa4_14: fullAdder PORT MAP (s(3,15), y_tmp(14,4), c(4,13), c(4,14), s(4,14));
y_tmp(15,4) <= x(15) AND y(4);
fa4_15: fullAdder PORT MAP (c(3,15), y_tmp(15,4), c(4,14), c(4,15), s(4,15));
-- row 5
y_tmp(0,5) <= x(0) AND y(5);
fa5_0: fullAdder PORT MAP (s(4,1), y_tmp(0,5), '0', c(5,0), s(5,0));
p(5) <= s(5,0);
y_tmp(1,5) <= x(1) AND y(5);
fa5_1: fullAdder PORT MAP (s(4,2), y_tmp(1,5), c(5,0), c(5,1), s(5,1));
y_tmp(2,5) <= x(2) AND y(5);
fa5_2: fullAdder PORT MAP (s(4,3), y_tmp(2,5), c(5,1), c(5,2), s(5,2));
y_tmp(3,5) <= x(3) AND y(5);
fa5_3: fullAdder PORT MAP (s(4,4), y_tmp(3,5), c(5,2), c(5,3), s(5,3));
y_tmp(4,5) <= x(4) AND y(5);
fa5_4: fullAdder PORT MAP (s(4,5), y_tmp(4,5), c(5,3), c(5,4), s(5,4));
y_tmp(5,5) <= x(5) AND y(5);
fa5_5: fullAdder PORT MAP (s(4,6), y_tmp(5,5), c(5,4), c(5,5), s(5,5));
y_tmp(6,5) <= x(6) AND y(5);
fa5_6: fullAdder PORT MAP (s(4,7), y_tmp(6,5), c(5,5), c(5,6), s(5,6));
y_tmp(7,5) <= x(7) AND y(5);
fa5_7: fullAdder PORT MAP (s(4,8), y_tmp(7,5), c(5,6), c(5,7), s(5,7));
y_tmp(8,5) <= x(8) AND y(5);
fa5_8: fullAdder PORT MAP (s(4,9), y_tmp(8,5), c(5,7), c(5,8), s(5,8));
y_tmp(9,5) <= x(9) AND y(5);
fa5_9: fullAdder PORT MAP (s(4,10), y_tmp(9,5), c(5,8), c(5,9), s(5,9));
y_tmp(10,5) <= x(10) AND y(5);
fa5_10: fullAdder PORT MAP (s(4,11), y_tmp(10,5), c(5,9), c(5,10), s(5,10));
y_tmp(11,5) <= x(11) AND y(5);
fa5_11: fullAdder PORT MAP (s(4,12), y_tmp(11,5), c(5,10), c(5,11), s(5,11));
y_tmp(12,5) <= x(12) AND y(5);
fa5_12: fullAdder PORT MAP (s(4,13), y_tmp(12,5), c(5,11), c(5,12), s(5,12));
y_tmp(13,5) <= x(13) AND y(5);
fa5_13: fullAdder PORT MAP (s(4,14), y_tmp(13,5), c(5,12), c(5,13), s(5,13));
y_tmp(14,5) <= x(14) AND y(5);
fa5_14: fullAdder PORT MAP (s(4,15), y_tmp(14,5), c(5,13), c(5,14), s(5,14));
y_tmp(15,5) <= x(15) AND y(5);
fa5_15: fullAdder PORT MAP (c(4,15), y_tmp(15,5), c(5,14), c(5,15), s(5,15));
-- row 6
y_tmp(0,6) <= x(0) AND y(6);
fa6_0: fullAdder PORT MAP (s(5,1), y_tmp(0,6), '0', c(6,0), s(6,0));
p(6) <= s(6,0);
y_tmp(1,6) <= x(1) AND y(6);
fa6_1: fullAdder PORT MAP (s(5,2), y_tmp(1,6), c(6,0), c(6,1), s(6,1));
y_tmp(2,6) <= x(2) AND y(6);
fa6_2: fullAdder PORT MAP (s(5,3), y_tmp(2,6), c(6,1), c(6,2), s(6,2));
y_tmp(3,6) <= x(3) AND y(6);
fa6_3: fullAdder PORT MAP (s(5,4), y_tmp(3,6), c(6,2), c(6,3), s(6,3));
y_tmp(4,6) <= x(4) AND y(6);
fa6_4: fullAdder PORT MAP (s(5,5), y_tmp(4,6), c(6,3), c(6,4), s(6,4));
y_tmp(5,6) <= x(5) AND y(6);
fa6_5: fullAdder PORT MAP (s(5,6), y_tmp(5,6), c(6,4), c(6,5), s(6,5));
y_tmp(6,6) <= x(6) AND y(6);
fa6_6: fullAdder PORT MAP (s(5,7), y_tmp(6,6), c(6,5), c(6,6), s(6,6));
y_tmp(7,6) <= x(7) AND y(6);
fa6_7: fullAdder PORT MAP (s(5,8), y_tmp(7,6), c(6,6), c(6,7), s(6,7));
y_tmp(8,6) <= x(8) AND y(6);
fa6_8: fullAdder PORT MAP (s(5,9), y_tmp(8,6), c(6,7), c(6,8), s(6,8));
y_tmp(9,6) <= x(9) AND y(6);
fa6_9: fullAdder PORT MAP (s(5,10), y_tmp(9,6), c(6,8), c(6,9), s(6,9));
y_tmp(10,6) <= x(10) AND y(6);
fa6_10: fullAdder PORT MAP (s(5,11), y_tmp(10,6), c(6,9), c(6,10), s(6,10));
y_tmp(11,6) <= x(11) AND y(6);
fa6_11: fullAdder PORT MAP (s(5,12), y_tmp(11,6), c(6,10), c(6,11), s(6,11));
y_tmp(12,6) <= x(12) AND y(6);
fa6_12: fullAdder PORT MAP (s(5,13), y_tmp(12,6), c(6,11), c(6,12), s(6,12));
y_tmp(13,6) <= x(13) AND y(6);
fa6_13: fullAdder PORT MAP (s(5,14), y_tmp(13,6), c(6,12), c(6,13), s(6,13));
y_tmp(14,6) <= x(14) AND y(6);
fa6_14: fullAdder PORT MAP (s(5,15), y_tmp(14,6), c(6,13), c(6,14), s(6,14));
y_tmp(15,6) <= x(15) AND y(6);
fa6_15: fullAdder PORT MAP (c(5,15), y_tmp(15,6), c(6,14), c(6,15), s(6,15));
-- row 7
y_tmp(0,7) <= x(0) AND y(7);
fa7_0: fullAdder PORT MAP (s(6,1), y_tmp(0,7), '0', c(7,0), s(7,0));
p(7) <= s(7,0);
y_tmp(1,7) <= x(1) AND y(7);
fa7_1: fullAdder PORT MAP (s(6,2), y_tmp(1,7), c(7,0), c(7,1), s(7,1));
y_tmp(2,7) <= x(2) AND y(7);
fa7_2: fullAdder PORT MAP (s(6,3), y_tmp(2,7), c(7,1), c(7,2), s(7,2));
y_tmp(3,7) <= x(3) AND y(7);
fa7_3: fullAdder PORT MAP (s(6,4), y_tmp(3,7), c(7,2), c(7,3), s(7,3));
y_tmp(4,7) <= x(4) AND y(7);
fa7_4: fullAdder PORT MAP (s(6,5), y_tmp(4,7), c(7,3), c(7,4), s(7,4));
y_tmp(5,7) <= x(5) AND y(7);
fa7_5: fullAdder PORT MAP (s(6,6), y_tmp(5,7), c(7,4), c(7,5), s(7,5));
y_tmp(6,7) <= x(6) AND y(7);
fa7_6: fullAdder PORT MAP (s(6,7), y_tmp(6,7), c(7,5), c(7,6), s(7,6));
y_tmp(7,7) <= x(7) AND y(7);
fa7_7: fullAdder PORT MAP (s(6,8), y_tmp(7,7), c(7,6), c(7,7), s(7,7));
y_tmp(8,7) <= x(8) AND y(7);
fa7_8: fullAdder PORT MAP (s(6,9), y_tmp(8,7), c(7,7), c(7,8), s(7,8));
y_tmp(9,7) <= x(9) AND y(7);
fa7_9: fullAdder PORT MAP (s(6,10), y_tmp(9,7), c(7,8), c(7,9), s(7,9));
y_tmp(10,7) <= x(10) AND y(7);
fa7_10: fullAdder PORT MAP (s(6,11), y_tmp(10,7), c(7,9), c(7,10), s(7,10));
y_tmp(11,7) <= x(11) AND y(7);
fa7_11: fullAdder PORT MAP (s(6,12), y_tmp(11,7), c(7,10), c(7,11), s(7,11));
y_tmp(12,7) <= x(12) AND y(7);
fa7_12: fullAdder PORT MAP (s(6,13), y_tmp(12,7), c(7,11), c(7,12), s(7,12));
y_tmp(13,7) <= x(13) AND y(7);
fa7_13: fullAdder PORT MAP (s(6,14), y_tmp(13,7), c(7,12), c(7,13), s(7,13));
y_tmp(14,7) <= x(14) AND y(7);
fa7_14: fullAdder PORT MAP (s(6,15), y_tmp(14,7), c(7,13), c(7,14), s(7,14));
y_tmp(15,7) <= x(15) AND y(7);
fa7_15: fullAdder PORT MAP (c(6,15), y_tmp(15,7), c(7,14), c(7,15), s(7,15));
-- row 8
y_tmp(0,8) <= x(0) AND y(8);
fa8_0: fullAdder PORT MAP (s(7,1), y_tmp(0,8), '0', c(8,0), s(8,0));
p(8) <= s(8,0);
y_tmp(1,8) <= x(1) AND y(8);
fa8_1: fullAdder PORT MAP (s(7,2), y_tmp(1,8), c(8,0), c(8,1), s(8,1));
y_tmp(2,8) <= x(2) AND y(8);
fa8_2: fullAdder PORT MAP (s(7,3), y_tmp(2,8), c(8,1), c(8,2), s(8,2));
y_tmp(3,8) <= x(3) AND y(8);
fa8_3: fullAdder PORT MAP (s(7,4), y_tmp(3,8), c(8,2), c(8,3), s(8,3));
y_tmp(4,8) <= x(4) AND y(8);
fa8_4: fullAdder PORT MAP (s(7,5), y_tmp(4,8), c(8,3), c(8,4), s(8,4));
y_tmp(5,8) <= x(5) AND y(8);
fa8_5: fullAdder PORT MAP (s(7,6), y_tmp(5,8), c(8,4), c(8,5), s(8,5));
y_tmp(6,8) <= x(6) AND y(8);
fa8_6: fullAdder PORT MAP (s(7,7), y_tmp(6,8), c(8,5), c(8,6), s(8,6));
y_tmp(7,8) <= x(7) AND y(8);
fa8_7: fullAdder PORT MAP (s(7,8), y_tmp(7,8), c(8,6), c(8,7), s(8,7));
y_tmp(8,8) <= x(8) AND y(8);
fa8_8: fullAdder PORT MAP (s(7,9), y_tmp(8,8), c(8,7), c(8,8), s(8,8));
y_tmp(9,8) <= x(9) AND y(8);
fa8_9: fullAdder PORT MAP (s(7,10), y_tmp(9,8), c(8,8), c(8,9), s(8,9));
y_tmp(10,8) <= x(10) AND y(8);
fa8_10: fullAdder PORT MAP (s(7,11), y_tmp(10,8), c(8,9), c(8,10), s(8,10));
y_tmp(11,8) <= x(11) AND y(8);
fa8_11: fullAdder PORT MAP (s(7,12), y_tmp(11,8), c(8,10), c(8,11), s(8,11));
y_tmp(12,8) <= x(12) AND y(8);
fa8_12: fullAdder PORT MAP (s(7,13), y_tmp(12,8), c(8,11), c(8,12), s(8,12));
y_tmp(13,8) <= x(13) AND y(8);
fa8_13: fullAdder PORT MAP (s(7,14), y_tmp(13,8), c(8,12), c(8,13), s(8,13));
y_tmp(14,8) <= x(14) AND y(8);
fa8_14: fullAdder PORT MAP (s(7,15), y_tmp(14,8), c(8,13), c(8,14), s(8,14));
y_tmp(15,8) <= x(15) AND y(8);
fa8_15: fullAdder PORT MAP (c(7,15), y_tmp(15,8), c(8,14), c(8,15), s(8,15));
-- row 9
y_tmp(0,9) <= x(0) AND y(9);
fa9_0: fullAdder PORT MAP (s(8,1), y_tmp(0,9), '0', c(9,0), s(9,0));
p(9) <= s(9,0);
y_tmp(1,9) <= x(1) AND y(9);
fa9_1: fullAdder PORT MAP (s(8,2), y_tmp(1,9), c(9,0), c(9,1), s(9,1));
y_tmp(2,9) <= x(2) AND y(9);
fa9_2: fullAdder PORT MAP (s(8,3), y_tmp(2,9), c(9,1), c(9,2), s(9,2));
y_tmp(3,9) <= x(3) AND y(9);
fa9_3: fullAdder PORT MAP (s(8,4), y_tmp(3,9), c(9,2), c(9,3), s(9,3));
y_tmp(4,9) <= x(4) AND y(9);
fa9_4: fullAdder PORT MAP (s(8,5), y_tmp(4,9), c(9,3), c(9,4), s(9,4));
y_tmp(5,9) <= x(5) AND y(9);
fa9_5: fullAdder PORT MAP (s(8,6), y_tmp(5,9), c(9,4), c(9,5), s(9,5));
y_tmp(6,9) <= x(6) AND y(9);
fa9_6: fullAdder PORT MAP (s(8,7), y_tmp(6,9), c(9,5), c(9,6), s(9,6));
y_tmp(7,9) <= x(7) AND y(9);
fa9_7: fullAdder PORT MAP (s(8,8), y_tmp(7,9), c(9,6), c(9,7), s(9,7));
y_tmp(8,9) <= x(8) AND y(9);
fa9_8: fullAdder PORT MAP (s(8,9), y_tmp(8,9), c(9,7), c(9,8), s(9,8));
y_tmp(9,9) <= x(9) AND y(9);
fa9_9: fullAdder PORT MAP (s(8,10), y_tmp(9,9), c(9,8), c(9,9), s(9,9));
y_tmp(10,9) <= x(10) AND y(9);
fa9_10: fullAdder PORT MAP (s(8,11), y_tmp(10,9), c(9,9), c(9,10), s(9,10));
y_tmp(11,9) <= x(11) AND y(9);
fa9_11: fullAdder PORT MAP (s(8,12), y_tmp(11,9), c(9,10), c(9,11), s(9,11));
y_tmp(12,9) <= x(12) AND y(9);
fa9_12: fullAdder PORT MAP (s(8,13), y_tmp(12,9), c(9,11), c(9,12), s(9,12));
y_tmp(13,9) <= x(13) AND y(9);
fa9_13: fullAdder PORT MAP (s(8,14), y_tmp(13,9), c(9,12), c(9,13), s(9,13));
y_tmp(14,9) <= x(14) AND y(9);
fa9_14: fullAdder PORT MAP (s(8,15), y_tmp(14,9), c(9,13), c(9,14), s(9,14));
y_tmp(15,9) <= x(15) AND y(9);
fa9_15: fullAdder PORT MAP (c(8,15), y_tmp(15,9), c(9,14), c(9,15), s(9,15));
-- row 10
y_tmp(0,10) <= x(0) AND y(10);
fa10_0: fullAdder PORT MAP (s(9,1), y_tmp(0,10), '0', c(10,0), s(10,0));
p(10) <= s(10,0);
y_tmp(1,10) <= x(1) AND y(10);
fa10_1: fullAdder PORT MAP (s(9,2), y_tmp(1,10), c(10,0), c(10,1), s(10,1));
y_tmp(2,10) <= x(2) AND y(10);
fa10_2: fullAdder PORT MAP (s(9,3), y_tmp(2,10), c(10,1), c(10,2), s(10,2));
y_tmp(3,10) <= x(3) AND y(10);
fa10_3: fullAdder PORT MAP (s(9,4), y_tmp(3,10), c(10,2), c(10,3), s(10,3));
y_tmp(4,10) <= x(4) AND y(10);
fa10_4: fullAdder PORT MAP (s(9,5), y_tmp(4,10), c(10,3), c(10,4), s(10,4));
y_tmp(5,10) <= x(5) AND y(10);
fa10_5: fullAdder PORT MAP (s(9,6), y_tmp(5,10), c(10,4), c(10,5), s(10,5));
y_tmp(6,10) <= x(6) AND y(10);
fa10_6: fullAdder PORT MAP (s(9,7), y_tmp(6,10), c(10,5), c(10,6), s(10,6));
y_tmp(7,10) <= x(7) AND y(10);
fa10_7: fullAdder PORT MAP (s(9,8), y_tmp(7,10), c(10,6), c(10,7), s(10,7));
y_tmp(8,10) <= x(8) AND y(10);
fa10_8: fullAdder PORT MAP (s(9,9), y_tmp(8,10), c(10,7), c(10,8), s(10,8));
y_tmp(9,10) <= x(9) AND y(10);
fa10_9: fullAdder PORT MAP (s(9,10), y_tmp(9,10), c(10,8), c(10,9), s(10,9));
y_tmp(10,10) <= x(10) AND y(10);
fa10_10: fullAdder PORT MAP (s(9,11), y_tmp(10,10), c(10,9), c(10,10), s(10,10));
y_tmp(11,10) <= x(11) AND y(10);
fa10_11: fullAdder PORT MAP (s(9,12), y_tmp(11,10), c(10,10), c(10,11), s(10,11));
y_tmp(12,10) <= x(12) AND y(10);
fa10_12: fullAdder PORT MAP (s(9,13), y_tmp(12,10), c(10,11), c(10,12), s(10,12));
y_tmp(13,10) <= x(13) AND y(10);
fa10_13: fullAdder PORT MAP (s(9,14), y_tmp(13,10), c(10,12), c(10,13), s(10,13));
y_tmp(14,10) <= x(14) AND y(10);
fa10_14: fullAdder PORT MAP (s(9,15), y_tmp(14,10), c(10,13), c(10,14), s(10,14));
y_tmp(15,10) <= x(15) AND y(10);
fa10_15: fullAdder PORT MAP (c(9,15), y_tmp(15,10), c(10,14), c(10,15), s(10,15));
-- row 11
y_tmp(0,11) <= x(0) AND y(11);
fa11_0: fullAdder PORT MAP (s(10,1), y_tmp(0,11), '0', c(11,0), s(11,0));
p(11) <= s(11,0);
y_tmp(1,11) <= x(1) AND y(11);
fa11_1: fullAdder PORT MAP (s(10,2), y_tmp(1,11), c(11,0), c(11,1), s(11,1));
y_tmp(2,11) <= x(2) AND y(11);
fa11_2: fullAdder PORT MAP (s(10,3), y_tmp(2,11), c(11,1), c(11,2), s(11,2));
y_tmp(3,11) <= x(3) AND y(11);
fa11_3: fullAdder PORT MAP (s(10,4), y_tmp(3,11), c(11,2), c(11,3), s(11,3));
y_tmp(4,11) <= x(4) AND y(11);
fa11_4: fullAdder PORT MAP (s(10,5), y_tmp(4,11), c(11,3), c(11,4), s(11,4));
y_tmp(5,11) <= x(5) AND y(11);
fa11_5: fullAdder PORT MAP (s(10,6), y_tmp(5,11), c(11,4), c(11,5), s(11,5));
y_tmp(6,11) <= x(6) AND y(11);
fa11_6: fullAdder PORT MAP (s(10,7), y_tmp(6,11), c(11,5), c(11,6), s(11,6));
y_tmp(7,11) <= x(7) AND y(11);
fa11_7: fullAdder PORT MAP (s(10,8), y_tmp(7,11), c(11,6), c(11,7), s(11,7));
y_tmp(8,11) <= x(8) AND y(11);
fa11_8: fullAdder PORT MAP (s(10,9), y_tmp(8,11), c(11,7), c(11,8), s(11,8));
y_tmp(9,11) <= x(9) AND y(11);
fa11_9: fullAdder PORT MAP (s(10,10), y_tmp(9,11), c(11,8), c(11,9), s(11,9));
y_tmp(10,11) <= x(10) AND y(11);
fa11_10: fullAdder PORT MAP (s(10,11), y_tmp(10,11), c(11,9), c(11,10), s(11,10));
y_tmp(11,11) <= x(11) AND y(11);
fa11_11: fullAdder PORT MAP (s(10,12), y_tmp(11,11), c(11,10), c(11,11), s(11,11));
y_tmp(12,11) <= x(12) AND y(11);
fa11_12: fullAdder PORT MAP (s(10,13), y_tmp(12,11), c(11,11), c(11,12), s(11,12));
y_tmp(13,11) <= x(13) AND y(11);
fa11_13: fullAdder PORT MAP (s(10,14), y_tmp(13,11), c(11,12), c(11,13), s(11,13));
y_tmp(14,11) <= x(14) AND y(11);
fa11_14: fullAdder PORT MAP (s(10,15), y_tmp(14,11), c(11,13), c(11,14), s(11,14));
y_tmp(15,11) <= x(15) AND y(11);
fa11_15: fullAdder PORT MAP (c(10,15), y_tmp(15,11), c(11,14), c(11,15), s(11,15));
-- row 12
y_tmp(0,12) <= x(0) AND y(12);
fa12_0: fullAdder PORT MAP (s(11,1), y_tmp(0,12), '0', c(12,0), s(12,0));
p(12) <= s(12,0);
y_tmp(1,12) <= x(1) AND y(12);
fa12_1: fullAdder PORT MAP (s(11,2), y_tmp(1,12), c(12,0), c(12,1), s(12,1));
y_tmp(2,12) <= x(2) AND y(12);
fa12_2: fullAdder PORT MAP (s(11,3), y_tmp(2,12), c(12,1), c(12,2), s(12,2));
y_tmp(3,12) <= x(3) AND y(12);
fa12_3: fullAdder PORT MAP (s(11,4), y_tmp(3,12), c(12,2), c(12,3), s(12,3));
y_tmp(4,12) <= x(4) AND y(12);
fa12_4: fullAdder PORT MAP (s(11,5), y_tmp(4,12), c(12,3), c(12,4), s(12,4));
y_tmp(5,12) <= x(5) AND y(12);
fa12_5: fullAdder PORT MAP (s(11,6), y_tmp(5,12), c(12,4), c(12,5), s(12,5));
y_tmp(6,12) <= x(6) AND y(12);
fa12_6: fullAdder PORT MAP (s(11,7), y_tmp(6,12), c(12,5), c(12,6), s(12,6));
y_tmp(7,12) <= x(7) AND y(12);
fa12_7: fullAdder PORT MAP (s(11,8), y_tmp(7,12), c(12,6), c(12,7), s(12,7));
y_tmp(8,12) <= x(8) AND y(12);
fa12_8: fullAdder PORT MAP (s(11,9), y_tmp(8,12), c(12,7), c(12,8), s(12,8));
y_tmp(9,12) <= x(9) AND y(12);
fa12_9: fullAdder PORT MAP (s(11,10), y_tmp(9,12), c(12,8), c(12,9), s(12,9));
y_tmp(10,12) <= x(10) AND y(12);
fa12_10: fullAdder PORT MAP (s(11,11), y_tmp(10,12), c(12,9), c(12,10), s(12,10));
y_tmp(11,12) <= x(11) AND y(12);
fa12_11: fullAdder PORT MAP (s(11,12), y_tmp(11,12), c(12,10), c(12,11), s(12,11));
y_tmp(12,12) <= x(12) AND y(12);
fa12_12: fullAdder PORT MAP (s(11,13), y_tmp(12,12), c(12,11), c(12,12), s(12,12));
y_tmp(13,12) <= x(13) AND y(12);
fa12_13: fullAdder PORT MAP (s(11,14), y_tmp(13,12), c(12,12), c(12,13), s(12,13));
y_tmp(14,12) <= x(14) AND y(12);
fa12_14: fullAdder PORT MAP (s(11,15), y_tmp(14,12), c(12,13), c(12,14), s(12,14));
y_tmp(15,12) <= x(15) AND y(12);
fa12_15: fullAdder PORT MAP (c(11,15), y_tmp(15,12), c(12,14), c(12,15), s(12,15));
-- row 13
y_tmp(0,13) <= x(0) AND y(13);
fa13_0: fullAdder PORT MAP (s(12,1), y_tmp(0,13), '0', c(13,0), s(13,0));
p(13) <= s(13,0);
y_tmp(1,13) <= x(1) AND y(13);
fa13_1: fullAdder PORT MAP (s(12,2), y_tmp(1,13), c(13,0), c(13,1), s(13,1));
y_tmp(2,13) <= x(2) AND y(13);
fa13_2: fullAdder PORT MAP (s(12,3), y_tmp(2,13), c(13,1), c(13,2), s(13,2));
y_tmp(3,13) <= x(3) AND y(13);
fa13_3: fullAdder PORT MAP (s(12,4), y_tmp(3,13), c(13,2), c(13,3), s(13,3));
y_tmp(4,13) <= x(4) AND y(13);
fa13_4: fullAdder PORT MAP (s(12,5), y_tmp(4,13), c(13,3), c(13,4), s(13,4));
y_tmp(5,13) <= x(5) AND y(13);
fa13_5: fullAdder PORT MAP (s(12,6), y_tmp(5,13), c(13,4), c(13,5), s(13,5));
y_tmp(6,13) <= x(6) AND y(13);
fa13_6: fullAdder PORT MAP (s(12,7), y_tmp(6,13), c(13,5), c(13,6), s(13,6));
y_tmp(7,13) <= x(7) AND y(13);
fa13_7: fullAdder PORT MAP (s(12,8), y_tmp(7,13), c(13,6), c(13,7), s(13,7));
y_tmp(8,13) <= x(8) AND y(13);
fa13_8: fullAdder PORT MAP (s(12,9), y_tmp(8,13), c(13,7), c(13,8), s(13,8));
y_tmp(9,13) <= x(9) AND y(13);
fa13_9: fullAdder PORT MAP (s(12,10), y_tmp(9,13), c(13,8), c(13,9), s(13,9));
y_tmp(10,13) <= x(10) AND y(13);
fa13_10: fullAdder PORT MAP (s(12,11), y_tmp(10,13), c(13,9), c(13,10), s(13,10));
y_tmp(11,13) <= x(11) AND y(13);
fa13_11: fullAdder PORT MAP (s(12,12), y_tmp(11,13), c(13,10), c(13,11), s(13,11));
y_tmp(12,13) <= x(12) AND y(13);
fa13_12: fullAdder PORT MAP (s(12,13), y_tmp(12,13), c(13,11), c(13,12), s(13,12));
y_tmp(13,13) <= x(13) AND y(13);
fa13_13: fullAdder PORT MAP (s(12,14), y_tmp(13,13), c(13,12), c(13,13), s(13,13));
y_tmp(14,13) <= x(14) AND y(13);
fa13_14: fullAdder PORT MAP (s(12,15), y_tmp(14,13), c(13,13), c(13,14), s(13,14));
y_tmp(15,13) <= x(15) AND y(13);
fa13_15: fullAdder PORT MAP (c(12,15), y_tmp(15,13), c(13,14), c(13,15), s(13,15));
-- row 14
y_tmp(0,14) <= x(0) AND y(14);
fa14_0: fullAdder PORT MAP (s(13,1), y_tmp(0,14), '0', c(14,0), s(14,0));
p(14) <= s(14,0);
y_tmp(1,14) <= x(1) AND y(14);
fa14_1: fullAdder PORT MAP (s(13,2), y_tmp(1,14), c(14,0), c(14,1), s(14,1));
y_tmp(2,14) <= x(2) AND y(14);
fa14_2: fullAdder PORT MAP (s(13,3), y_tmp(2,14), c(14,1), c(14,2), s(14,2));
y_tmp(3,14) <= x(3) AND y(14);
fa14_3: fullAdder PORT MAP (s(13,4), y_tmp(3,14), c(14,2), c(14,3), s(14,3));
y_tmp(4,14) <= x(4) AND y(14);
fa14_4: fullAdder PORT MAP (s(13,5), y_tmp(4,14), c(14,3), c(14,4), s(14,4));
y_tmp(5,14) <= x(5) AND y(14);
fa14_5: fullAdder PORT MAP (s(13,6), y_tmp(5,14), c(14,4), c(14,5), s(14,5));
y_tmp(6,14) <= x(6) AND y(14);
fa14_6: fullAdder PORT MAP (s(13,7), y_tmp(6,14), c(14,5), c(14,6), s(14,6));
y_tmp(7,14) <= x(7) AND y(14);
fa14_7: fullAdder PORT MAP (s(13,8), y_tmp(7,14), c(14,6), c(14,7), s(14,7));
y_tmp(8,14) <= x(8) AND y(14);
fa14_8: fullAdder PORT MAP (s(13,9), y_tmp(8,14), c(14,7), c(14,8), s(14,8));
y_tmp(9,14) <= x(9) AND y(14);
fa14_9: fullAdder PORT MAP (s(13,10), y_tmp(9,14), c(14,8), c(14,9), s(14,9));
y_tmp(10,14) <= x(10) AND y(14);
fa14_10: fullAdder PORT MAP (s(13,11), y_tmp(10,14), c(14,9), c(14,10), s(14,10));
y_tmp(11,14) <= x(11) AND y(14);
fa14_11: fullAdder PORT MAP (s(13,12), y_tmp(11,14), c(14,10), c(14,11), s(14,11));
y_tmp(12,14) <= x(12) AND y(14);
fa14_12: fullAdder PORT MAP (s(13,13), y_tmp(12,14), c(14,11), c(14,12), s(14,12));
y_tmp(13,14) <= x(13) AND y(14);
fa14_13: fullAdder PORT MAP (s(13,14), y_tmp(13,14), c(14,12), c(14,13), s(14,13));
y_tmp(14,14) <= x(14) AND y(14);
fa14_14: fullAdder PORT MAP (s(13,15), y_tmp(14,14), c(14,13), c(14,14), s(14,14));
y_tmp(15,14) <= x(15) AND y(14);
fa14_15: fullAdder PORT MAP (c(13,15), y_tmp(15,14), c(14,14), c(14,15), s(14,15));
-- row 15
y_tmp(0,15) <= x(0) AND y(15);
fa15_0: fullAdder PORT MAP (s(14,1), y_tmp(0,15), '0', c(15,0), s(15,0));
p(15) <= s(15,0);
y_tmp(1,15) <= x(1) AND y(15);
fa15_1: fullAdder PORT MAP (s(14,2), y_tmp(1,15), c(15,0), c(15,1), s(15,1));
y_tmp(2,15) <= x(2) AND y(15);
fa15_2: fullAdder PORT MAP (s(14,3), y_tmp(2,15), c(15,1), c(15,2), s(15,2));
y_tmp(3,15) <= x(3) AND y(15);
fa15_3: fullAdder PORT MAP (s(14,4), y_tmp(3,15), c(15,2), c(15,3), s(15,3));
y_tmp(4,15) <= x(4) AND y(15);
fa15_4: fullAdder PORT MAP (s(14,5), y_tmp(4,15), c(15,3), c(15,4), s(15,4));
y_tmp(5,15) <= x(5) AND y(15);
fa15_5: fullAdder PORT MAP (s(14,6), y_tmp(5,15), c(15,4), c(15,5), s(15,5));
y_tmp(6,15) <= x(6) AND y(15);
fa15_6: fullAdder PORT MAP (s(14,7), y_tmp(6,15), c(15,5), c(15,6), s(15,6));
y_tmp(7,15) <= x(7) AND y(15);
fa15_7: fullAdder PORT MAP (s(14,8), y_tmp(7,15), c(15,6), c(15,7), s(15,7));
y_tmp(8,15) <= x(8) AND y(15);
fa15_8: fullAdder PORT MAP (s(14,9), y_tmp(8,15), c(15,7), c(15,8), s(15,8));
y_tmp(9,15) <= x(9) AND y(15);
fa15_9: fullAdder PORT MAP (s(14,10), y_tmp(9,15), c(15,8), c(15,9), s(15,9));
y_tmp(10,15) <= x(10) AND y(15);
fa15_10: fullAdder PORT MAP (s(14,11), y_tmp(10,15), c(15,9), c(15,10), s(15,10));
y_tmp(11,15) <= x(11) AND y(15);
fa15_11: fullAdder PORT MAP (s(14,12), y_tmp(11,15), c(15,10), c(15,11), s(15,11));
y_tmp(12,15) <= x(12) AND y(15);
fa15_12: fullAdder PORT MAP (s(14,13), y_tmp(12,15), c(15,11), c(15,12), s(15,12));
y_tmp(13,15) <= x(13) AND y(15);
fa15_13: fullAdder PORT MAP (s(14,14), y_tmp(13,15), c(15,12), c(15,13), s(15,13));
y_tmp(14,15) <= x(14) AND y(15);
fa15_14: fullAdder PORT MAP (s(14,15), y_tmp(14,15), c(15,13), c(15,14), s(15,14));
y_tmp(15,15) <= x(15) AND y(15);
fa15_15: fullAdder PORT MAP (c(14,15), y_tmp(15,15), c(15,14), c(15,15), s(15,15));
p(16) <= s(15,1);
p(17) <= s(15,2);
p(18) <= s(15,3);
p(19) <= s(15,4);
p(20) <= s(15,5);
p(21) <= s(15,6);
p(22) <= s(15,7);
p(23) <= s(15,8);
p(24) <= s(15,9);
p(25) <= s(15,10);
p(26) <= s(15,11);
p(27) <= s(15,12);
p(28) <= s(15,13);
p(29) <= s(15,14);
p(30) <= s(15,15);
p(31) <= c(15,15);
END v1;
---------------------------------------
-- end of VHDL code for mutl4X4 circuit
---------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------
-- VHDL code for Complex MAC
-- (multiplier accumulators)
-- at STRUCTURE LEVEL
--------------------------------
--##############################
--#Library of Complex MAC
--##############################
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY bitlib;
USE bitlib.bit_pack.all;
--##############################
--#Entity of Complex MAC
--##############################
ENTITY c_mac_gate IS
PORT (
clk, clr : IN bit; -- input
x_real : IN bit_vector(15 downto 0); -- input
x_imag : IN bit_vector(15 downto 0); -- input
y_real : IN bit_vector(15 downto 0); -- input
y_imag : IN bit_vector(15 downto 0); -- input
s_real : OUT bit_vector(15 downto 0); -- output
s_imag : OUT bit_vector(15 downto 0); -- output
ovf : OUT bit); -- output
END c_mac_gate;
--###########################################################
--# Implementing using the complex MAC at structure level
--###########################################################
ARCHITECTURE gate OF c_mac_gate IS
--######################
--#Function Declaration
--######################
--######################
--#Procedure Declaration
--######################
--######################
--#Component Declaration
--######################
COMPONENT expanding_range
PORT (
a: IN bit_vector(31 DOWNTO 0); -- Inputs
z: OUT bit_vector(31 DOWNTO 0) ); -- Outputs
END COMPONENT;
COMPONENT data_preprocess16
PORT (d: IN bit_vector(15 downto 0); -- input
sign: IN bit; -- input <the sign bit: used for selecting 2's complement or not
q: OUT bit_vector(15 downto 0)); -- outputs
END COMPONENT;
COMPONENT data_preprocess32
PORT (d: IN bit_vector(31 downto 0); -- input
sign: IN bit; -- input <the sign bit: used for selecting 2's complement or not
q: OUT bit_vector(31 downto 0)); -- outputs
END COMPONENT;
COMPONENT mutl16X16Circuit
PORT (
x, y : IN bit_vector(15 downto 0); -- inputs
p: OUT bit_vector(31 downto 0)); -- outputs
END COMPONENT;
COMPONENT two_s_complement32
PORT (
a: IN bit_vector(31 DOWNTO 0); -- Inputs
z: OUT bit_vector(31 DOWNTO 0) ); -- Outputs
END COMPONENT;
COMPONENT adder32
PORT (a, b: IN bit_vector(31 DOWNTO 0); ci: IN bit; -- Inputs
s: OUT bit_vector(31 DOWNTO 0); co: OUT bit); -- Outputs
END COMPONENT;
COMPONENT d_ff32s
PORT (d: IN bit_vector(31 DOWNTO 0); -- inputs
clk: IN bit; -- inputs
clr: IN bit; -- inputs
q: OUT bit_vector(31 DOWNTO 0); -- outputs
qn:OUT bit_vector(31 DOWNTO 0) := "11111111111111111111111111111111"); -- outputs
END COMPONENT;
COMPONENT ovfCircuit
PORT (
acc_ovf: IN bit; -- input
sum_ovf: IN bit; -- input
clr: IN bit; -- input
ovf: OUT bit); -- output
END COMPONENT;
--######################
--#Signal Declaration
--######################
SIGNAL x_real_vec : bit_vector(15 downto 0);
SIGNAL x_imag_vec : bit_vector(15 downto 0);
SIGNAL y_real_vec : bit_vector(15 downto 0);
SIGNAL y_imag_vec : bit_vector(15 downto 0);
SIGNAL s_real_vec : bit_vector(31 downto 0);
SIGNAL s_imag_vec : bit_vector(31 downto 0);
SIGNAL real_product_vec1: bit_vector(31 downto 0);
SIGNAL real_product_vec2: bit_vector(31 downto 0);
SIGNAL real_product_vec1_proper: bit_vector(31 downto 0);
SIGNAL real_product_vec2_proper: bit_vector(31 downto 0);
SIGNAL real_product_vec2_proper_comp: bit_vector(31 downto 0);
SIGNAL imag_product_vec1: bit_vector(31 downto 0);
SIGNAL imag_product_vec2: bit_vector(31 downto 0);
SIGNAL imag_product_vec1_proper: bit_vector(31 downto 0);
SIGNAL imag_product_vec2_proper: bit_vector(31 downto 0);
SIGNAL real_result_vec : bit_vector(31 downto 0);
SIGNAL imag_result_vec : bit_vector(31 downto 0);
SIGNAL real_result_vec_wide : bit_vector(31 downto 0);
SIGNAL imag_result_vec_wide : bit_vector(31 downto 0);
SIGNAL s_real_sum_vec: bit_vector(31 downto 0);
SIGNAL s_imag_sum_vec: bit_vector(31 downto 0);
SIGNAL s_real_sum_new: bit_vector(31 downto 0);
SIGNAL s_imag_sum_new: bit_vector(31 downto 0);
SIGNAL result_real_co : bit ;
SIGNAL result_imag_co : bit ;
SIGNAL sum_real_co : bit ;
SIGNAL sum_imag_co : bit ;
SIGNAL tmp_vec1_32 : bit_vector(31 downto 0);
SIGNAL tmp_vec2_32 : bit_vector(31 downto 0);
SIGNAL real_product1_sign: bit;
SIGNAL real_product2_sign: bit;
SIGNAL imag_product1_sign: bit;
SIGNAL imag_product2_sign: bit;
SIGNAL acc_ovf : bit ; -- [-1, 1) ovf
SIGNAL sum_ovf : bit ; -- [-16,16) ovf
BEGIN
-- get proper format(2's complement or not)
x_real_converter : data_preprocess16 PORT MAP (x_real, x_real(15), x_real_vec);
x_imag_converter : data_preprocess16 PORT MAP (x_imag, x_imag(15), x_imag_vec);
y_real_converter : data_preprocess16 PORT MAP (y_real, y_real(15), y_real_vec);
y_imag_converter : data_preprocess16 PORT MAP (y_imag, y_imag(15), y_imag_vec);
-- get real and imag partial product
mul_real_product1: mutl16X16Circuit PORT MAP (x_real_vec, y_real_vec, real_product_vec1);
mul_real_product2: mutl16X16Circuit PORT MAP (x_imag_vec, y_imag_vec, real_product_vec2);
mul_imag_product1: mutl16X16Circuit PORT MAP (x_real_vec, y_imag_vec, imag_product_vec1);
mul_imag_product2: mutl16X16Circuit PORT MAP (x_imag_vec, y_real_vec, imag_product_vec2);
-- get partial product sign
real_product1_sign <= x_real(15) XOR y_real(15);
real_product2_sign <= x_imag(15) XOR y_imag(15);
imag_product1_sign <= x_real(15) XOR y_imag(15);
imag_product2_sign <= x_imag(15) XOR y_real(15);
-- get proper format(2's complement or not)
real_product1_converter : data_preprocess32 PORT MAP (real_product_vec1, real_product1_sign, real_product_vec1_proper);
real_product2_converter : data_preprocess32 PORT MAP (real_product_vec2, real_product2_sign, real_product_vec2_proper);
imag_product1_converter : data_preprocess32 PORT MAP (imag_product_vec1, imag_product1_sign, imag_product_vec1_proper);
imag_product2_converter : data_preprocess32 PORT MAP (imag_product_vec2, imag_product2_sign, imag_product_vec2_proper);
-- calculate the multiplication results
complement_2s_1: two_s_complement32 PORT MAP (real_product_vec2_proper, real_product_vec2_proper_comp);
adder32_1: adder32 PORT MAP (real_product_vec1_proper, real_product_vec2_proper_comp, '0', real_result_vec, result_real_co);
adder32_2: adder32 PORT MAP (imag_product_vec1_proper, imag_product_vec2_proper, '0', imag_result_vec, result_imag_co);
-- expanding range
expand_real: expanding_range PORT MAP (real_result_vec, real_result_vec_wide);
expand_imag: expanding_range PORT MAP (imag_result_vec, imag_result_vec_wide);
-- calculate the summation
adder32_3: adder32 PORT MAP (s_real_sum_new, real_result_vec_wide, '0', s_real_sum_vec, sum_real_co);
adder32_4: adder32 PORT MAP (s_imag_sum_new, imag_result_vec_wide, '0', s_imag_sum_vec, sum_imag_co);
-- generate output signal
d_ff32s_1: d_ff32s PORT MAP (s_real_sum_vec, clk, clr, s_real_sum_new, tmp_vec1_32);
d_ff32s_2: d_ff32s PORT MAP (s_imag_sum_vec, clk, clr, s_imag_sum_new, tmp_vec2_32);
s_real <= s_real_sum_new(31)&s_real_sum_new(26 downto 12);
s_imag <= s_imag_sum_new(31)&s_imag_sum_new(26 downto 12);
-- generate ovf signal
acc_ovf <= ((NOT s_real_sum_new(31)) AND (s_real_sum_new(30) OR s_real_sum_new(29) OR s_real_sum_new(28) OR s_real_sum_new(27)))
OR (s_real_sum_new(31) AND ((NOT s_real_sum_new(30)) OR (NOT s_real_sum_new(29)) OR (NOT s_real_sum_new(28)) OR (NOT s_real_sum_new(27))))
OR ((NOT s_imag_sum_new(31)) AND (s_imag_sum_new(30) OR s_imag_sum_new(29) OR s_imag_sum_new(28) OR s_imag_sum_new(27)))
OR (s_imag_sum_new(31) AND ((NOT s_imag_sum_new(30)) OR (NOT s_imag_sum_new(29)) OR (NOT s_imag_sum_new(28)) OR (NOT s_imag_sum_new(27))));
sum_ovf <= (NOT (s_real_sum_new(31) XOR real_result_vec_wide(31)))
AND (s_real_sum_vec(31) XOR real_result_vec_wide(31))
AND (NOT (s_imag_sum_new(31) XOR imag_result_vec_wide(31)))
AND (s_imag_sum_vec(31) XOR imag_result_vec_wide(31));
ovfCircuit1: ovfCircuit PORT MAP(acc_ovf, sum_ovf, clr, ovf);
END gate;
------------------------------------
-- end of VHDL code for Complex MAC
-- (multiplier accumulators)
-- at STRUCTURE LEVEL
------------------------------------
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