Test Bench <VHDL Source Code> of Special Counter

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-- Test bench for special counter
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LIBRARY my_vhdl;
USE my_vhdl.count9;


ENTITY spc_test IS
END spc_test;

ARCHITECTURE tester OF spc_test IS
        COMPONENT count9
        PORT (
          rstn, clk, up, down : IN bit;                          -- input
          data                : IN bit_vector(8 downto 0);       -- input
        
          count_ff            : INOUT bit_vector(8 downto 0);    -- output
          carry_out           : OUT bit;                         -- output
          borrow_out          : OUT bit;                         -- output
          parity              : OUT bit);                        -- output        
        END COMPONENT;

        SIGNAL rstn_t      : bit := '1';
        SIGNAL clk_t       : bit := '0';
        SIGNAL up_t        : bit := '0';
        SIGNAL down_t      : bit := '0';
        SIGNAL data_t      : bit_vector(8 downto 0) := "111110101";
        SIGNAL count_ff_t  : bit_vector(8 downto 0);
        SIGNAL carry_out_t : bit;
        SIGNAL borrow_out_t: bit;
        SIGNAL parity_t    : bit;
                
BEGIN
        data_t <= "000000011" AFTER 310 ns, "000001010" AFTER 500 ns;
        clk_t <= NOT clk_t AFTER 20 ns;     -- generate clock
        up_t <= '1' AFTER 50 ns, '0' AFTER 300 ns, '1' AFTER 600 ns, '0' AFTER 800 ns;  -- testing up,down:00, 10, 01, 11, 00
        down_t <= '1' AFTER 350 ns, '0' AFTER 670 ns;
        rstn_t <= '0' AFTER 1 ns, '1' AFTER 2 ns, '0' AFTER 390 ns, '1' AFTER 410 ns, '0' AFTER 610 ns, '1' AFTER 650 ns ;
        spc1: count9 PORT MAP (rstn_t,clk_t,up_t,down_t,data_t,count_ff_t,carry_out_t,borrow_out_t,parity_t);
END tester;

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-- END of Test bench for special counter
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