Projects of Digital Design
Instructor: Dr.
Serpen
Project #1: Modeling & Simulating SR-Latch Using VHDL
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Use a conditional assignment statement
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Use the characteristic equation
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Use two logic gates
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Test the functionality with appropriate test patterns
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TOOLS: VHDL, Mentor Graphics
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Source Code
Project #2: Design & VHDL Implementation of a Special Purpose
Counter
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Design a 9-bit up-by-3 and down-by-5 counter using a VHDL structural model.
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Outputs from the counter are even parity, carry, borrow and counter value,
while the inputs to the counter are clock, 9-bit data to be loaded in parallel,
a bit to command counting up and a second bit to command counting down.
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When UP & DOWN = "00", the counter is parallel loaded with input DATA.
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When UP & DOWN = "01", the counter is decreased by 5.
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When UP & DOWN = "10", the counter is increased by 3.
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When UP & DOWN = "11", the counter is not changed.
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RSTn is the asynchoronous reset signal to be connected to all asynchronous
reset inputs of flip-flops.
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CLK input signal is also connected to clock inputs of all flip-flops.
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Simulate and Test the designed model using appropriate test bench.
Project #3: Design and VHDL Implementation of a Non-pipelined Complex
Multiplier
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Many digital signal processing algorithms, including FFT, filtering/equalization,
and demodulation, making use of multiplier accumulators (MAC). A
complex MAC operates on two sequences of complex number {xi} and {yi}.
The MAC multiplies corresponding elements of the sequences and accumulates
the sum of the products.
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Each complex number is represented in Cartesian form, consisting of a real
and an imaginary part. If we are given two complex numbers x and y, their
product is a complex number p, calculated as follows:
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p_real = x_real x y_real - x_imag x y_imag
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p_imag = x_real x y_imag + x_imag x y_real
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The sum of x and y is a complex number s calculated as follows:
s_real = x_real + y_real
s_imag = x_imag + y_imag
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MAC calculates its results by taking successive pairs of complex numbers,
one each from the two input sequences, forming their complex product and
adding it to an accumulator register. The accumulator is initially
cleared to zero and is reset after each pair of sequences has been processed.
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Data is represented with a 16 bit, two's fixed -point binary representation.
Each of the real and imaginary parts of the two complex numbers and the
complex output of the MAC uses the same representation where bit 15 is
the sign bit and the binary point is assumed to be between bits 15 and
14. This format will facilitate numbers in the range -1 (inclusive)
to +1 (exclusive) with a resolution of 2*exp(-15). This raises the
possibility of overflow occurring while summing a sequence of numbers,
so we include an overflow status signal in the design. Overflow can
occur in two cases. First, intermediate partial sums may fall outside the
range -1 to +1. We can reduce the likelihood of this happening by
expanding the range used to represent intermediate results to -16 to +16.
However, if an intermediate sum falls outside of the expanded range, the
summation for the entire sequence is in error, so the overflow signal must
be set. It remains set until the accumulator is cleared, indicating
the end of the summation. The second overflow case happens if the
final sum falls outside the range of values representable by the MAC output.
This may be a transient condition, since a subsequent product, when added
to the sum, may bring the sum back in range. Assert the overflow
signal only during a cycle in which the final sum is out of range, rather
than
latching the overflow until the end of summation.
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Simulate and Test the designed model using appropriate test bench.
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